Lakshmi Boppana

IoT based smart security and home automation system

Internet of Things (IoT) conceptualizes the idea of remotely connecting and monitoring real world objects (things) through the Internet [1]. When it comes to our house, this concept can be aptly incorporated to make it smarter, safer and automated. This IoT project focuses on building a smart wireless home security system which sends alerts to the owner by using Internet in case of any trespass and raises an alarm optionally. Besides, the same can also be utilized for home automation by making use of the same set of sensors. The leverage obtained by prefering this system over the similar kinds of existing systems is that the alerts and the status sent by the wifi connected microcontroller managed system can be received by the user on his phone from any distance irrespective of whether his mobile phone is connected to the internet. The microcontroller used in the current prototype is the TI-CC3200 Launchpad board which comes with an embedded micro-controller and an onboard Wi-Fi shield making use of which all the elctrical appliances inside the home can be controlled and managed.

FPGA implementation of vedic floating point multiplier

Most of the scientific operation involve floating point computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a critical role in any digital design. Even though various multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic mathematics involves application of 16 sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered in this work. An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been made use of while implementing these algorithms and a resource utilization and timing performance based comparison has also been made.

Energy efficient m- level LEACH protocol

Wireless Sensor Networks (WSNs) comprise of large number of sensor nodes, which sense and measure various physical phenomena related parameters and transmit the measured data towards the base station by making use of the neighbouring nodes acting as relay nodes. In order to extend the lifetime of a WSN application, it is necessary to distribute the energy dissipated among the nodes evenly in the network and improve the overall system performance. The lifetime of network depends on the underlying routing protocol. This paper presents various energy-efficient routing protocols being widely used. A performance comparison of direct transmission protocol, MTE protocol and LEACH protocol and improved LEACH and multi-level LEACH protocols like MLEACH protocol, DD-LEACH protocol and TL-LEACH protocol is presented. This work also proposes an energy efficient and improved multi-level LEACH protocol and DD-TL-LEACH protocol. For the purpose of simulation analysis, the NS-3 simulation platform has been made use of.

FPGA implementation of Itoh-Tsujii inversion algorithm

Elliptic Curve Cryptography (ECC) has been gaining popularity due to its shorter key size requirements. It uses arithmetic operations including addition, subtraction, multiplication and inversion in finite fields. For an efficient implementation of ECC, it is very important to carry out these operations faster using lesser resources. The in version operation consumes most of the time and more resources. The Itoh-Tsujii algorithm can be used to carry out the computation of multiplicative inverse by making use of Brauer addition chains in less time. This work presents an FPGA implementation of the multiplicative inversion for the key lengths of 194-, 233-, and 384- bits. A resource comparison for these key lengths is also made. This work uses Sunar-Koc multiplier for the finite field, GF(2m) multiplication.

FPGA implementation of multipliers for ECC

Scalar Multiplication(SM) is the most frequently used operation in Elliptic Curve Cryptography(ECC). The efficiency of an ECC based system depends on the efficient implementation of SM. The type of basis used while designing a cryptosystem determines the space and time complexities. We implemented two multipliers based on Optimal Normal Basis of type II(ONB) and polynomial basis. This work uses Karatsuba and Sunar-Koc algorithms. The hardware implementations of both the multipliers have been carried out for different key lengths: 243, 251, and 270 bits. The FPGA device used for hardware implementation is XC6VLX240T(Virtex-6). The synthesis results are compared qualitatively in terms of hardware complexities for these key lengths.

Implementations of Sunar-Koc multiplier using FPGA platform and WSN node

In elliptic curve cryptography (ECC), multiplication operations are used frequently. In order to realize an efficient ECC implementation for large key lengths, it is necessary to choose an algorithm using which it is possible to compute these multiplication operations at higher speeds. This work presents two different implementations of Sunar-Koc multiplier, using FPGA device and a WSN node. This work considered the key lengths 173- bit, 194- bit and 233- bit in both the FPGA and WSN node implementations of the multiplier. A MEMSIC IRIS WSN node has been used during the implementation and a resource comparison, comprising of storage requirements, energy consumption and clock cycles for different key lengths, is made. The obtained FPGA synthesis results have also been compared.

Modulation switching in OFDM for WiMAX through Rayleigh fading channel using GNU radio

This paper presents modulation switching in OFDM for WiMAX specifications by considering Raleigh fading channel using GNU Radio companion. WiMAX technology is considered as the most eminent solution able to allow a Broadband wireless Access (BWA) in metropolitan areas with a merer installation and lower cost. OFDM is the fundamental block in WiMAX PHY layer. Modulation switching is performed in WiMAX to amend the network performance in the case of Non-LoS communication. This work proposes a script in Python to build a block which selects the modulation scheme to be used in OFDM. The results show that a selector block automatically adopts the modulation scheme to be used, while an OFDM system is in operation.

FPGA implementation of IEEE-754 floating point Karatsuba multiplier

The floating point arithmetic, specifically multiplication, is a widely used computational operation in many scientific and signal processing applications. In general, the IEEE-754 single-precision multiplier requires a 23 × 23 mantissa multiplication and the double-precision multiplier requires a large 52 × 52 mantissa multiplier to obtain the final result. This computation exists as a limit on both area and performance bounds of this operation. A lot of multiplication algorithms have been developed during the past decades. In this paper, the two of the popular algorithms, namely, Booth and Karatsuba (Normal and Recursive) multipliers have been implemented, and a performance comparison is also made. The algorithms have been implemented on an uniform reconfigurable FPGA platform providing a comparison of FPGA resources utilized and execution speeds. The recursive Karatsuba is the best performing algorithm among the algorithms.

FPGA implementation of RC-4T and WPA

Security is an important feature to be included in the field of wireless communications, where the transmission and reception need to be unassailable. Every wireless device needs to adopt a security model which may be complex or simple to make the communication impregnable. The algorithm to be chosen for the final implementation depends on the characteristics of the device. Applications requiring higher security should employ devices having computational capabilities and good amount of hardware and those applications that do not need to have tight security can compromise with the hardware resources and the ability of the micro-controller/microprocessor. In this work two security models namely, the RC-4 with the Toeplitz hash algorithm (RC-4T) and the Wi-Fi protected Access (WPA) have been compared in terms of hardware complexity and combinational delay. Both of these algorithms have been implemented using the XilinxVirtex-6q FPGA device for the comparison based on resource utilization and delays. Toeplitz hash function has been used along with RC-4 algorithm for the generation of the key stream thus making the security model more robust as compared to the traditional WEP.

Implementation of Toeplitz Hash based RC-4 in WSN

Certain Wireless sensor network (WSN) applications such as military and e- health care require the inter-node communication to be secure. The tiny WSN nodes have limited computational power, memory and finite energy source. These constraints restrict the implementation of highly secure models on the devices as they demand more memory and involve compute intensive operations. Several protocols have been designed for providing different security levels with varying strengths at the expense of the amount of hardware and computational power of the processor in the WSN node. In wireless equivalent privacy (WEP) model static keys are generated for the XOR operation with the plain text in the encryption process. This work proposes a new security model that provides dynamic keys to the encryption/decryption stages. A model for the proposed scheme has been developed using nesC and the same has been implemented on a IRIS WSN node. The WSN implementation of the proposed security model has been compared with those of WEP, WiFi Protected access (WPA) based on memory usage and execution time.