Lakshmi N. Chakrapani

Trimaran: an infrastructure for research in instruction-level parallelism

Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor architecture supporting novel features such as predication, control and data speculation and compiler controlled management of the memory hierarchy. Trimaran also consists of a full suite of analysis and optimization modules, as well as a graph-based intermediate language. Optimizations and analysis modules can be easily added, deleted or bypassed, thus facilitating compiler optimization research. Similarly, computer architecture research can be conducted by varying the HPL-PD machine via the machine description language HMDES. Trimaran also provides a detailed simulation environment and a flexible performance monitoring environment that automatically tracks the machine as it is varied.

Probabilistic system-on-a-chip architectures

Parameter variations, noise susceptibility, and increasing energy dissipation of cmos devices have been recognized as major challenges in circuit and microarchitecture design in the nanometer regime. Among these, parameter variations and noise susceptibility are increasingly causing cmos devices to behave in an “unreliable” or “probabilistic” manner. To address these challenges, a shift in design paradigm from current-day deterministic designs to “statistical” or “probabilistic” designs is deemed inevitable. To respond to this need, in this article, we introduce and study an entirely novel family of probabilistic architectures: the probabilistic system-on-a-chip (psoc). psoc architectures are based on cmos devices rendered probabilistic due to noise, referred to as probabilistic CMOS or PCMOS devices. We demonstrate that in addition to harnessing the probabilistic behavior of pcmos devices, psoc architectures yield significant improvements, both in energy consumed as well as performance in the context of probabilistic or randomized applications with broad utility. All of our application and architectural savings are quantified using the product of the energy and performance, denoted (energy × performance): The pcmos-based gains are as high as a substantial multiplicative factor of over 560 when compared to a competing energy-efficient cmos-based realization. Our architectural design is application specific and involves navigating design space spanning the algorithm (application), its architecture (psoc), and the probabilistic technology (pcmos).

Advocating Noise as an Agent for Ultra-Low Energy Computing: Probabilistic Complementary Metal-Oxide-Semiconductor Devices and Their Characteristics

Noise immunity and low-energy computing have become limiting factors in the semiconductor roadmap as transistor feature sizes shrink. The subject of our study is the probabilistic switch, implemented in the complementary metal–oxide–semiconductor (CMOS) domain, referred to as a probabilistic CMOS (PCMOS) switch, whose behavior is rendered probabilistic by noise. In conducting this study, we are motivated by the possibility of using such probabilistic switches to realize ultra-low energy computing. Based on PCMOS switches realized using 0.5 and 0.25 µm processes, we present detailed analytical models, subsequently verified through HSpice simulations. We consider the thermal noise and power supply noise as our sources for probabilistic behavior. Through one interesting aspect of the study, we characterize the effects of the noise sampling frequency and the output sampling frequency on probabilistic behavior. Finally, we briefly outline the opportunity that such probabilistic switches offer to ultra low-energy computing through the concept of a probabilistic system-on-a-chip (PSoC) architecture (that is based on PCMOS switches); such architectures can achieve significant energy savings and performance improvements at the application level.

The emerging power crisis in embedded processors: what can a poor compiler do?

It is widely acknowledged that even as VLSI technology advances, there is a looming crisis that is an important obstacle to the widespread deployment of mobile embedded devices, namely that of power. This problem can be tackled at many levels like devices, logic, operating systems, micro-architecture and compiler. While there have been various proposals for specific compiler optimizations for power, there has not been any attempt to systematically map out the space for possible improvements. In this paper, we quantitatively characterize the limits of what a compiler can do in optimizing for power using precise modeling of a state-of-the-art embedded processor in conjunction with a robust compiler. We provide insights to how compiler optimizations interact with the internal workings of a processor from the perspective of power consumption. The goal is to point out the promising and not so promising directions of work in this area, to guide the future compiler designer.

Probabilistic CMOS Technology: A Survey and Future Directions

Highly scaled CMOS devices in the nanoscale regime would inevitably exhibit statistical or probabilistic behavior. Such behavior is due to process variations and other perturbations such as noise. Therefore current circuit design methodologies, which depend on the existence of deterministic and uniform devices with no consideration for either power consumption or probabilistic behavior, would no longer be sufficient to design robust circuits. To help overcome this challenge, CMOS devices have been characterized with probabilistic behavior (probabilistic CMOS or PCMOS devices) at several levels: from foundational principles to analytical modeling, simulation, fabrication and measurement, as well as innovative approaches to harnessing PCMOS devices in system-on-a-chip architectures which can implement a wide range of applications. This paper presents a broad overview of our contributions in the domain of PCMOS, and outline ongoing work and future challenges in this area

A probabilistic Boolean logic for energy efficient circuit and system design

We introduce probabilistic design, a methodology to design circuits using gates with probabilistic behavior. Probabilistic design is of great value, since the international technology roadmap for semiconductors (ITRS) forecasts that devices and interconnect are likely to suffer from frequent transient and permanent failures, as a consequence of technology scaling. We first provide the theoretical basis for probabilistic design, rooted in a novel Probabilistic Boolean Logic (pbl). By combining the properties of pbl with the properties of noise susceptible cmos devices, we derive design principles and demonstrate that probabilistic design is a viable methodology to design circuits using gates with probabilistic behavior, which has been shown to be a useful approach for implementing ultra low-energy circuit designs.

Realizing Ultra-low Energy Application Specific SoC Architectures through Novel Probabilistic CMOS (PCMOS) Technology

1 This work was supported in part by DARPA Seedling Contract #F30602-02-2-0124.

Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design

Highly scaled CMOS devices in the nanoscale regime would inevitably exhibit statistical or probabilistic behavior. Such behavior is caused by process variations, and other perturbations such as noise. Current circuit design methodologies, which depend on the existence of “deterministic” devices that behave consistently in temporal and spatial contexts do not admit considerations for probabilistic behavior. Admittedly, power or energy consumption as well as the associated heat dissipation are proving to be impediments to the continued scaling (down) of device sizes. To help overcome these challenges, we have characterized CMOS devices with probabilistic behavior (probabilistic CMOS or PCMOS devices) at several levels: from foundational principles to analytical modeling, simulation, fabrication, measurement as well as exploration of innovative approaches towards harnessing them through system-on-a-chip architectures. We have shown that such architectures can implement a wide range of probabilistic and cognitive applications. All of these architectures yield significant energy savings by trading probability with which the device operates correctly—lower the probability of correctness, the greater the energy savings. In addition to these PCMOS based innovations, we will also survey probabilistic arithmetic—a novel framework through which traditional computing units such as adders and multipliers can be deliberately designed to be erroneous, while being characterized by a well-defined probability of correctness. We demonstrate that in return for erroneous behavior, significant energy and performance gains can be realized through probabilistic arithmetic (units)—over a factor of 4.62X in the context of an FIR filter used in a H.264 video decoding—where the gains are quantified through the energy-performance product (or EPP). These gains are achieved through a systematic probabilistic designmethodology enabled by a design space spanning the probability of correctness of the arithmetic units, and their associated energy savings.

Power-performance trade-offs in second level memory used by an ARM-like RISC architecture

Power consumption is an important dimension in microprocessor and digital system design. This is especially true in the embedded setting where microprocessors have to operate without the luxury of a large power supply or cooling structures. In this paper, we describe an infrastructure setup for the study of power-performance tradeoffs in microprocessor architecture and compiler optimizations. This infrastructure distinguishes itself from those already proposed in the literature in its use of power estimations based on synthesis of the architecture and the full integration of a well-established optimizing compiler framework. We present some preliminary results where we show how the circuit level and architectural techniques can be combined to save overall system power. In particular we reduce the clock frequency and supply voltage of level two memory accesses (circuit level technique) and compensate for the resulting increase in the completion time by implementing a non-blocking store buffer (architectural technique) resulting in up to 39 % less power and up to 28 % less energy on a set of candidate benchmarks.