Larry M. Augustin

Specification and analysis of system architecture using Rapide

Rapide is an event-based, concurrent, object-oriented language specifically designed for prototyping system architectures. Two principle design goals are: (1) to provide constructs for defining executable prototypes of architectures and (2) to adopt an execution model in which the concurrency, synchronization, dataflow, and timing properties of a prototype are explicitly represented. This paper describes the partially ordered event set (poset) execution model and outlines with examples some of the event-based features for defining communication architectures and relationships between architectures. Various features of Rapide are illustrated by excerpts from a prototype of the X/Open distributed transaction processing reference architecture. >

Partial orderings of event sets and their application to prototyping concurrent, timed systems

Rapide is a concurrent object-oriented language specifically designed for prototyping large concurrent systems. One of the principle design goals has been to adopt a computation model in which the synchronization, concurrency, dataflow, and timing aspects of a prototype are explicitly represented and easily accessible both to the prototype itself and to the prototyper. This paper describes the partially ordered event set (poset) computation model, and the features of Rapide for using posets in reactive prototypes and for automatically checking posets. Some critical issues in the implementation of Rapide are described and our experience with them is summarized. An example prototyping scenario illustrates uses of the poset computation model.

Hardware Design and Simulation in Val-VHDL

I A Tutorial Introduction to VAL.- 1 Introduction.- 1.1 Comparative Simulation With VAL.- 1.2 Why Extend VHDL?.- 1.3 Future Directions.- 1.4 Notation and Conventions.- 2 An Overview of VAL.- 2.1 Entity Annotations.- 2.1.1 Entity State Model.- 2.1.2 Assumptions.- 2.1.3 Statements and Processes.- 2.1.4 Timing Behavior.- 2.2 Architecture Annotations.- 2.3 Configuration Annotations.- 3 Timing Models.- 3.1 The VHDL Timing Model.- 3.1.1 Unit Delay.- 3.1.2 Transport Delay.- 3.1.3 Inertial Delay.- 3.1.4 Justification.- 3.2 The VAL Timing Model.- 3.2.1 Anticipatory Semantics.- 3.2.2 Assertions.- 4 Designing With Annotations.- 4.1 Introduction.- 4.2 Traffic Light Controller.- 4.2.1 Specification.- 4.2.2 Implementation.- 4.3 Stack.- 4.3.1 Specification.- 4.3.2 Implementation.- 4.4 Summary.- II Examples.- 5 Crazy AND Gate.- 5.1 Requirements.- 5.2 Entity Declaration.- 5.3 Commentary.- 5.3.1 Altering the Specification.- 5.3.2 Altering the Implementation.- 6 D-Type Flip-flop.- 6.1 Requirements.- 6.2 Entity Declaration.- 6.3 Commentary.- 7 Traffic Light Controller.- 7.1 Requirements.- 7.2 Entity Declaration.- 7.3 Architecture.- 7.4 Simulation Results.- 8 Stack.- 8.1 Requirements.- 8.2 Entity Declaration.- 8.3 Entity Architecture.- 8.4 Commentary.- 9 Water Heater Controller.- 9.1 Requirements.- 9.2 Entity Declaration.- 9.3 Implementation.- 9.4 Simulation Results.- 10 CPU Example.- 10.1 Requirements.- 10.1.1 Instruction level specification.- 10.1.2 Register transfer level specifications.- 10.1.3 Gate level specifications.- 10.1.4 Hierarchy of components.- 10.2 CPU Annotation methodology.- 10.2.1 Entity annotation.- 10.2.2 Mapping.- 10.3 VHDL description.- III The VAL Language Reference Manual.- 11 Lexical Elements.- 11.1 Character Set.- 11.2 Lexical Elements, Separators, and Delimiters.- 11.3 Identifiers.- 11.4 Literals.- 11.5 Comments.- 11.6 Annotations.- 11.7 Reserved Words.- 11.8 Allowable Replacements of Characters.- 11.9 BNF Notation.- 12 Design Units.- 12.1 Entity Annotations.- 12.2 Architecture Annotations.- 12.3 Configuration Annotations.- 13 State Model.- 13.1 State Model Declaration.- 13.2 State Model Type.- 14 Declarations.- 14.1 Types, Subtypes, Constants, Aliases and Use Clauses.- 14.2 Assumptions.- 14.3 Objects.- 14.4 Macros.- 15 Names and Expressions.- 15.1 Timed Expressions.- 15.2 Intervals.- 15.3 Function Call.- 16 Statements.- 16.1 Assertions.- 16.2 Drive Statement.- 16.3 Guards.- 16.4 Select.- 16.5 Generate.- 16.6 Macro Call.- 16.7 Null.- 17 Mapping Annotations.- 18 Configuration Annotations.- 19 Miscellaneous.- 19.1 Package.- 19.2 Scope and Visibility.- 19.2.1 Declarative Region and Scope of Declarations.- 19.2.2 Visibility.- 19.2.3 Use Clause.- 19.2.4 The Context of Overload Resolution.- 19.3 Attributes.- IV Transformer Implementation Guide.- 20 The VAL Transformer.- 20.1 Transformation Principles.- 20.2 Translation Methodology.- 20.3 Transformation Algorithm.- 20.3.1 Generation of Translation Skeleton.- 20.3.2 Transformation to Core VAL.- 20.3.3 Code Generation.- 20.3.4 Architecture Annotations.- 20.3.5 Configuration Annotations.- 20.4 Summary.- V Appendix.- A Syntax Summary.- A.1 Lexical Elements.- A.2 Syntax.- B CPU : VHDL description.- B.1 One bit alu.- B.2 16 bit alu.- B.3 One bit buffer.- B.4 12 bit buffer.- B.5 16 bit buffer.- B.6 CPU.- B.7 CPU configuration.- B.8 CPU support package.- B.9 CPU test bench.- B.10 Or arrays.- B.11 PLA.- B.12 One bit one output register.- B.13 16 bit one output register.- B.14 One bit two output register.- B.15 16 bit two output register.

Verification of VHDL designs using VAL

VAL (VHDL Annotation Language) uses a small number of language constructs to annotate VHDL (VHSIC Hardware Description Language) hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. The result is a simple but expressive language extension of VHDL with possible applications to automatic checking of VHDL simulations, hierarchical design, and automatic verification of hardware designs in VHDL. An overview is given of design checking using VAL. VAL is described in detail and it is shown how VAL annotations are used to generate constraints on a VHDL simulation. A brief overview of the VAL transformer demonstrates the feasibility of the design. Some observations based on experience with VAL to date and areas for future work are considered.<<ETX>>

Timing models in VAL/VHDL

A detailed description is given of the timing model of VHDL (VHSIC hardware description language). VHDL uses a two-level timing model based on discrete event simulation. Timed assignment statements are preemptive, and two forms of preemption are supported in the language: inertial and transport. The author describes the VAL (VHDL annotation language) timing model and features of VAL designed to work with the VHDL timing model. VAL introduces assertions that understand the two-level timing framework in VHDL. In contrast to the preemptive assignment of VHDL, VAL models the same behavior using only anticipatory semantics (no preemption). The anticipatory model enables VAL descriptions to be treated as constraints on the input/output behavior of a device that may be directly translated into predicates. The author demonstrates by a simple example the application of formal techniques for manipulating these predicates.<<ETX>>

An overview of VAL

VAL (VHDL Annotation Language) provides a small number of new language constructs to annotate VHDL hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. Annotations are expressed as parallel processes that accept streams of input signals and generate constraints on output streams. VAL views signals as streams of values ordered by time. Generalized timing expressions allow the designer to refer to relative points on a stream. No concept of preemptive delayed assignment or inertial delay are needed when referring to different relative points in time on a stream. The VAL abstract state model permits abstract data types to be used in specifying history dependent device behavior. Annotations placed inside a VHDL architecture define detailed correspondences between the behavior specification and architecture. The result is a simple but expressive language extension of VHDL with possible applications to automatic checking of VHDL simulations, hierarchical design, and automatic verification of hardware designs in VHDL.

D- Type Flip-flop

We wish to specify the entity behavior of a D-type flip-flop with timing parameters. The flip-flop under consideration is generic in three timing parameters, the set-up time (SETUP), the hold time (HOLD), and the propagation delay (DELAY). It has two inputs, D (data) and Clk (the triggering signal or clock); and two outputs, the state (Q) and its complement (Qbar). At each falling edge of the clock, the flip-flop updates its state to the input value, with a delay specified by the DELAY generic parameter. For the flip-flop to work properly, the input data must be stable from time SETUP before the calling edge of Clk to time HOLD (for example 5ns) after the falling edge of Clk.

Traffic Light Controller

This example of a traffic light controller is from “Introduction to VLSI” design by Mead and Conway [19] (pages 85-88). We reproduce here the informal specification as stated in the reference.

Designing with Annotations

This chapter illustrates some ways of using VAL annotations in the design process; that is, the process of specifying an entity, and subsequently refining a specification into an architecture of simpler component entities. The top-down approach from specification to implementation is emphasized throughout. The examples given here are intended to be suggestive of various uses of annotations, and are not exhaustive nor complete in any sense. The design process is still very much an area for research, and VAL annotations simply present the designer with a new tool, some of whose applications are shown here.

Water Heater Controller

The water heater controller example is taken from the problem set of the Fourth International Workshop on Software Specification and Design, April 3-4, 1987, Monterey, California: Problem #2. Heating System. (Based on a problem by S. White presented to 1984 Embedded Computer System Requirement Workshop.)