Lars Philipson

A communication structure for a multiprocessor computer with distributed global memory

An experimental multiprocessor computer was designed and built in order to explore the feasibility of certain internal communication mechanisms. The system consisted of seven processing elements, each containing a part of the global memory connected to a local bus. For each processor the global memory is seen as one single, linearly addressable structure. The processing elements were all connected to a common, global bus, consisting of three separate busses in order to increase the capacity. A bus selection unit was designed, capable of making a unique bus selection for each request, within a fraction of a memory cycle. The experiments have shown that communication structures based on distributed global memory and global bus systems can be used efficiently for medium scale systems.

Interaction semantics of a symbolic layout editor for parameterized modules

An interactive graphical editor for parameterized layout generators, based on symbolic layout, is discussed. One basic idea is to have built-in rules, corresponding to basic knowledge about elementary things in VLSI design, in order to make the tool behave as an experienced partner to the designer. It was found that the fundamental problem was not to implement but to select a proper set of rules to define the semantics of the tool. The problem was attacked by actually implementing various experimental versions and using them to create layout. These experiments and the conclusions are summarized. For example, the fundamental importance of proper mechanisms to explicitly express geometrical constraints, such as pitch-matching, is shown. It is also shown how parameterization can be introduced in a user-friendly and natural way through the graphical, symbolic layout view. >

Movie-an interactive environment for silicon compilation tools

Movie is a special-purpose environment for silicon compilation tools, providing services in the same way that an operating system does to application problems. Movie also contains the functionality of an advanced module generator tool. An internal design representation was developed that allows a combination of hierarchically parameterized module generators, symbolic layout, and interactive graphical editing. This design representation has been formalized into a representation language with well-defined semantics. Movie provides a set of operations, formally defined using the representation language, for use by the tools. A set of instantiation mechanisms ensure certain correctness of the result independently of the tools and closes the design-verification loop. Movie was designed to take advantage of fast color graphics, special-purpose data structures and incremental updating to achieve interactivity with immediate visual feedback by real-time animation. By integration high-level tools, a hierarchy of levels of abstraction is maintained. Silicon compilation systems based on Movie can be expected to be open-ended, transparent, and highly interactive. >

A Layered Emulator for Design Evaluation of MIMD Multiprocessors with Shared Memory

In the design and evaluation of new multiprocessor structures it is necessary to make experiments to explore the consequences of various decisions, e.g. the dynamic interaction between hardware, system software and executing parallel programs. When the target architecture is based on VLSI implementation, it is especially necessary to make the experiments prior to implementation.

Implementation of a Pascal based parallel language for a multiprocessor computer

This paper reports the work on implementing a parallel version of Pascal on a small scale multiprocessor computer. A few simple primitives were included to support parallel programming. The code generation, linking and loading procedures are described. An overview of the hardware is included. Finally some programming experience with the system is reported.

VLSI based design principles for MIMD multiprocessor computers with distributed memory management

Design principles for MIMD multiprocessor computers with virtual memory based on a common, global and uniform logical address space, supporting parallel, procedural languages such as Ada (Ada is a registered trademark of the US Government, AJPO), are discussed. The major design issues are identified and suggested solutions given, the most important of which are distributed, associative address translation, and local mechanisms supporting efficient resource allocation policies to reduce over-all communication costs. Arguments are given for using shared memory and bus-based global communication. Some preliminary studies of bus-based intercommunication schemes, parallel language implementation, capacity simulation and VLSI implementation are reviewed, as well as a number of existing experimental and commercial multiprocessors. Finally an experimental system for evaluation of different mechanisms and policies in systems of the suggested type is outlined.

A simple Ada compiler invalidation test

This small program tests some of the not-so-easily implemented features of Ada. Among the things tested are separate compilation, overloading, generics, aggregates, tasking and various real time facilities. The program can be used to get a quick assessment of the completeness of a non validated Ada compiler.

Computer Analysis of Motor Unit Discharge Patterns

Motor unit analysis in the clinical EMG laboratory usually is based on recordings of EMG activity, in which individual motor unit potentials are considered to belong to the same motor unit if they have similar shape. Each motor unit then can be characterized by the amplitude, duration and number of phases of its potential. By examining several potentials from the same unit and calculating the mean values of these variables, the quantitative characterization can be made more reliable. Even with more sophisticated EMG equipment the procedure is, in principle, the same.

CONTROLLER SYNTHESIS AND VERIFICATION

This chapter focuses on synthesis and verification of control units. One of the key issues in synthesis is the ability to explore the design space. One step toward design space exploration is the results presented here in control architecture synthesis that enables exploration of a range of control architectures. Another step is the use of a compiled cell approach to the technology mapping problem in control unit logic synthesis. The verification of the synthesized control unit is also an important issue. A new approach is presented that, using a combination of propositional temporal logic verifier and sequential logic extraction, has made it possible to verify formally the layout of a control unit against the specification.