Lars Schor

Towards a zero-configuration wireless sensor network architecture for smart buildings

Todays buildings account for a large fraction of our energy consumption. In an effort to economize scarce fossil fuels on earth, sensor networks are a valuable tool to increase the energy efficiency of buildings without severely reducing our quality of life. Within a smart building many sensors and actuators are interconnected to form a control system. Nowadays, the deployment of a building control system is complicated because of different communication standards. In this paper, we present a web services-based approach to integrate resource constrained sensor and actuator nodes into IP-based networks. A key feature of our approach is its capability for automatic service discovery. For this purpose, we implemented an API to access services on sensor nodes following the architectural style of representational state transfer (REST). We implemented a prototype application based on TinyOS 2.1 on a custom sensor node platform with 8 Kbytes of RAM and an IEEE 802.15.4 compliant radio transceiver.

Scenario-based design flow for mapping streaming applications onto on-chip many-core systems

The next generation of embedded software has high performance requirements and is increasingly dynamic. Multiple applications are typically sharing the system, running in parallel in different combinations, starting and stopping their individual execution at different moments in time. The different combinations of applications are forming system execution scenarios. In this paper, we present the distributed application layer, a scenario-based design flow for mapping a set of applications onto heterogeneous on-chip many-core systems. Applications are specified as Kahn process networks and the execution scenarios are combined into a finite state machine. Transitions between scenarios are triggered by behavioral events generated by either running applications or the run-time system. A set of optimal mappings are precalculated during design-time analysis. Later, at run-time, hierarchically organized controllers monitor behavioral events, and apply the precalculated mappings when starting new applications. To handle architectural failures, spare cores are allocated at design-time. At run-time, the controllers have the ability to move all processes assigned to a faulty physical core to a spare core. Finally, we apply the proposed design flow to design and optimize a picture-in-picture software.

Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs

As single-processor systems are ceasing to scale effectively, multi-processor systems are becoming more and more popular. While there are many challenges of designing multi-processor systems in hardware, writing efficient parallel applications that utilize the computing capability of multiple processors may reveal to be even more challenging. In this paper, we introduce a framework that allows to efficiently execute applications expressed as Kahn process networks on multi-processor systems using protothreads and windowed FIFOs. We show that application developers can use this framework to achieve considerable speed-ups on the Cell Broadband Engine without needing to write architecture-specific code.

Thermal-aware system analysis and software synthesis for embedded multi-processors

Nowadays, the reliability and performance of modern embedded multi-processor systems is threaten by the everincreasing power densities in integrated circuits, and a new additional goal of software synthesis is to reduce the peak temperature of the system. However, in order to perform thermal-aware mapping optimization, the timing and thermal characteristics of every candidate mapping have to be analyzed. While the task of analyzing timing characteristics of design alternatives has been extensively investigated in recent years, there is still a lack of methods for accurate and fast thermal analysis. In order to obtain desired evaluation times, the system has to be simulated at a high ab]ion level. This often results in a loss of accuracy, mainly due to missing knowledge of systems characteristics. This paper addresses this challenge and presents methods to automatically calibrate high-level thermal evaluation methods. Furthermore, the viability of the methods for automated model calibration is illustrated by means of a novel high-level thermal evaluation method.

Worst-Case Temperature Guarantees for Real-Time Applications on Multi-core Systems

Due to increased on-chip power density, multi-core systems face various thermal issues. In particular, exceeding a certain threshold temperature can reduce the systems performance and reliability. Therefore, when designing a real-time application with non-deterministic workload, the designer has to be aware of the maximum possible temperature of the system. This paper proposes an analytic method to calculate an upper bound on the worst-case peak temperature of a real-time system with multiple cores generated under all possible scenarios of task executions. In order to handle a broad range of uncertainties, task arrivals are modeled as periodic event streams with jitter and delay. Finally, the proposed method is applied to a multi-core ARM platform and our results are validated in various case studies.

Multi-objective mapping optimization via problem decomposition for many-core systems

Due to the trend of many-core systems for dynamic multimedia applications, the problem size of mapping optimization gets bigger than ever making conventional meta-heuristics no longer effective. Thus, in this paper, we propose a problem decomposition approach for large scale optimization problems. We basically follow the divide-and-conquer concept, in which a large scale problem is divided into several sub-problems. To remove the inter-relationship between sub-problems, proper abstraction is applied. The divided sub-problems can be solved either in parallel or in a sequence. The mapping optimization problem on dynamic many-core systems is decomposed and solved separately considering the system state and architectural hierarchy. Experimental evaluations with several examples prove that the proposed technique outperforms the conventional meta-heuristics both in optimality and diversity of the optimized pareto curve.

Exploiting the parallelism of heterogeneous systems using dataflow graphs on top of OpenCL

Programming heterogeneous systems has been greatly simplified by OpenCL, which provides a common low-level API for a large variety of compute devices. However, many low-level details, including data transfer, task scheduling, or synchronization, must still be managed by the application designer. Often, it is desirable to program heterogeneous systems in a higher-level language, making the developing process faster and less error-prone. In this paper, we introduce a framework to efficiently execute applications specified as synchronous dataflow graphs (SDF) on heterogeneous systems by means of OpenCL. In our approach, actors are embedded into OpenCL kernels and data channels are automatically instantiated to improve memory access latencies and end-to-end performance. The multi-level parallelism resulting from the hierarchical structure of heterogeneous systems is exploited by applying two techniques. Pipeline and task parallelism are used to distribute the application to the different compute devices and data-parallelism is used to concurrently process independent actor firings or even output tokens in a SIMD fashion. We demonstrate that the proposed framework can be used by application designers to efficiently exploit the parallelism of heterogeneous systems without writing low-level architecture dependent code.

Predictability for timing and temperature in multiprocessor system-on-chip platforms

High computational performance in multiprocessor system-on-chips (MPSoCs) is constrained by the ever-increasing power densities in integrated circuits, so that nowadays MPSoCs face various thermal issues. For instance, high chip temperatures may lead to long-term reliability concerns and short-term functional errors. Therefore, the new challenge in designing embedded real-time MPSoCs is to guarantee the final performance and correct function of the system, considering both functional and non-functional properties. One way to achieve this is by ruling out mapping alternatives that do not fulfill requirements on performance or peak temperature already in early design stages. In this article, we propose a thermal-aware optimization framework for mapping real-time applications onto MPSoC platforms. The performance and temperature of mapping candidates are evaluated by formal temporal and thermal analysis models. To this end, analysis models are automatically generated during design space exploration, based on the same specifications as used for software synthesis. The analysis models are automatically calibrated with performance data reflecting the execution of the system on the target platform. The data is automatically obtained prior to design space exploration based on a set of benchmark mappings. Case studies show that the performance and temperature requirements are often conflicting goals and optimizing them together leads to major benefits in terms of a guaranteed and predictable high performance.

Thermal-Aware Task Assignment for Real-Time Applications on Multi-Core Systems

The reduced feature size of electronic systems and the demand for high performance lead to increased power densities and high chip temperatures, which in turn reduce the system reliability. Thermal-aware task allocation and scheduling algorithms are promising approaches to reduce the peak temperature of multi-core systems with real-time constraints. However, as long as the worst-case chip temperature is not incorporated into system analysis, no guarantees on the performance can be given. This paper explores thermal-aware task assignment strategies for real-time applications with non-deterministic workload that are running on a multi-core system. In particular, tasks are assigned to the multi-core system so that the worst-case chip temperature is minimized and all real-time deadlines are met. Each core has its own clock domain and the static assigned frequency corresponds to the minimum operation frequency such that no real-time deadline is missed. Finally, we show that the proposed temperature minimization problem can efficiently be solved by metaheuristics.

Dynamic many-process applications on many-tile embedded systems and HPC clusters

In the next decade, a growing number of scientific and industrial applications will require power-efficient systems providing unprecedented computation, memory, and communication resources. A promising paradigm foresees the use of heterogeneous many-tile architectures. The resulting computing systems are complex: they must be protected against several sources of faults and critical events, and application programmers must be provided with programming paradigms, software environments and debugging tools adequate to manage such complexity. The EURETILE (European Reference Tiled Architecture Experiment) consortium conceived, designed, and implemented: 1- an innovative many-tile, many-process dynamic fault-tolerant programming paradigm and software environment, grounded onto a lightweight operating system generated by an automated software synthesis mechanism that takes into account the architecture and application specificities; 2- a many-tile heterogeneous hardware system, equipped with a high-bandwidth, low-latency, point-to-point 3D-toroidal interconnect. The inter-tile interconnect processor is equipped with an experimental mechanism for systemic fault-awareness; 3- a full-system simulation environment, supported by innovative parallel technologies and equipped with debugging facilities. We also designed and coded a set of application benchmarks representative of requirements of future HPC and Embedded Systems, including: 4- a set of dynamic multimedia applications and 5- a large scale simulator of neural activity and synaptic plasticity. The application benchmarks, compiled through the EURETILE software tool-chain, have been efficiently executed on both the many-tile hardware platform and on the software simulator, up to a complexity of a few hundreds of software processes and hardware cores.