Lars Wanhammar

Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm

In this work, a new algorithm called nonrecursive signed common subexpression elimination (NR-SCSE) is discussed, and several applications in the area of multiplierless finite-impulse response (FIR) filters are developed. While the recursive utilization of a common subexpression generates a high logic depth into the digital structure, the NR-SCSE algorithm allows the designer to overcome this problem by using each subexpression once. The paper presents a complete description of the algorithm, and a comparison with two other well-known options: the graph synthesis, and the classical common subexpression elimination technique. Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.

Extended results for minimum-adder constant integer multipliers

By introducing simplifications to multiplier graphs we extend the previous work on minimum adder multipliers to five adders and show that this is enough to express all coefficients up to 19 bits. The average savings are more than 25% for 19 bits compared with CSD multipliers. The simplifications include addition reordering and vertex reduction to see that different graphs can generate the same coefficient sets. Thus, fewer graphs need to be evaluated. A classification of the graphs reduces the effort to search the coefficient space further.

ILP modelling of the common subexpression sharing problem

Subexpression sharing is an important implementation issue when one data is multiplied with many constants or a sum of products is computed. By modelling the subexpression sharing problem using integer linear programming (ILP) an optimal solution can be found. Further, the model can be directly incorporated with the design of algorithms that have linear design constraints, e.g., linear-phase FIR filters. The proposed method is compared with previously reported algorithms. It produces better results than other subexpression sharing methods, even though it is still not comparable with the optimal method based on graph representation. However, the possibility to expand the ILP model beyond subexpression sharing is discussed. This would then produce identical results to the optimal adder graph method.

A hardware efficient control of memory addressing for high-performance FFT processors

The conventional memory organization of fast Fourier transform (FFT) processors is based on Cohens (1976) scheme. Compared with this scheme, our scheme reduces the hardware complexity of address generation by about 50% while improving the memory access speed. Much power consumption in memory is saved since only half of the memory is activated during memory access, and the number of coefficient access is reduced to a minimum by using a new ordering of FFT butterflies. Therefore, the new scheme is a superior solution to constructing high-performance FFT processors.

A pipeline FFT processor

We discuss the design and implementation of a high-speed, low power 1024-point pipeline FFT processor. Key features are flexible internal data length and a novel processing element. The FFT processor, which is implemented in a standard 0.35 /spl mu/m CMOS process, is efficient in terms of power consumption and chip area.

High-speed recursive digital filters based on the frequency-response masking approach

The frequency-response masking approach for highspeed recursive infinite-impulse response (IIR) digital filters is introduced. In this approach, the overall filter consists of a periodic model filter, its power-complementary periodic filter, and two masking filters. The model filters are composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. The transfer functions of the all-pass filters are functions of z/sup M/, which implies that the maximal sample frequency for the overall filter is M times that of the corresponding conventional IIR filter. The maximal sample frequency can be increased to an arbitrary level for arbitrary bandwidths. The overall filter can be designed by separately optimizing the model and masking filters with the aid of conventional approximation techniques. The obtained overall filter also serves as a good initial filter for further optimization. Both nonlinear-phase and approximately linear-phase filters are considered. By using the new approach, the potential problems of pole-zero cancellations, which are inherent in algorithm transformation techniques, are avoided. Further, robust filters under finite-arithmetic conditions can always be obtained by using wave-digital all-pass filters and nonrecursive FIR filters. Several design examples are included illustrating the properties of the new filters.

Improved multiple constant multiplication using a minimum spanning tree

Recently, a novel technique for the multiple constant multiplication (MCM) problem using minimum spanning trees (MSTs) has been proposed. The approach works by finding simple differences between the coefficients to realize and then applying the same method to the differences (which is an MCM problem as well). Each iteration is divided into two steps. First, finding a minimum spanning tree in the graph describing the differences between the coefficients. Second, as each edge in the graph may correspond to more than one difference, one difference is selected for each edge in the MST. Generally, both these stages have multiple solutions. The aim of this work is to more closely study how the MST and the differences should be selected to give better total results. It is also discussed how the two stages in each iteration may be joined into one problem.

Two-channel digital and hybrid analog/digital multirate filter banks with very low-complexity analysis or synthesis filters

Multirate filter banks make use of analysis and synthesis filter banks. This paper introduces two-channel digital and hybrid analog/digital multirate filter banks where either the analysis or synthesis filters have a very low complexity. Such filter banks find application, for example, in high-speed analog-to digital converters where it is essential to minimize the complexity of the discrete-time or analog filters. The proposed digital filter banks are approximately perfect reconstruction (PR) filter banks, whereas the hybrid analog/digital filter banks can be chosen to be either approximately PR or approximately perfect magnitude reconstruction filter banks. The design is performed by first optimizing the digital or analog analysis filters and then, with the analysis filters fixed, optimizing the digital synthesis filters. This design procedure makes it possible to obtain analysis filters of very low order and complexity. The overall complexity is also low. Further, the proposed filter banks are, in all cases, very easy to design by making use of well-known and reliable optimization techniques; in particular, as small distortion and aliasing as desired are readily obtained because they are controlled in a linear programming problem. Several design examples are included, illustrating the properties of the proposed filter banks.

A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity

Multiple constant multiplication (MCM) has been an active research area for the last decade. Most work so far have only considered the number of additions to realize a number of constant multiplications with the same input. In this work, we consider the number of full and half adder cells required to realize those additions, and a novel complexity measure is proposed. The proposed complexity measure can be utilized for all types of constant operations based on shifts, additions and subtractions. Based on the proposed complexity measure a novel MCM algorithm is presented. Simulations show that compared with previous algorithms, the proposed MCM algorithm have a similar number of additions while the number of full adder cells are significantly reduced.

A novel approach to multiple constant multiplication using minimum spanning trees

In this work a novel approach to multiple constant multiplication based on minimum spanning trees is proposed. Each required coefficient is assigned to a vertex in a graph. The vertices are connected with weighted edges, where each edge weight corresponds to the number of adders required to derive one of the coefficient from the previous. The graph can be used to solve for the minimum spanning tree, which leads to a realization with a small number of adders. The optimal minimum spanning tree can be found in polynomial time. It is also possible to add extra constraints to the spanning tree, such as limited out-degree (corresponds to fan-out) and limited tree height (corresponds to delay). These problems are harder to solve, but there are good heuristics available. It is shown by simulation that the performance of the proposed algorithm is comparable with recently published algorithms.