László Dózsa

Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures

Defect properties of undoped low-pressure chemical-vapor-deposited (LPCVD) polysilicon films have been investigated by capacitance techniques on a simple metal-oxide-semiconductor (MOS) capacitor structure. The results show that the effective density of bulk and interface trap states is almost independent of the deposition pressure. After reducing the polysilicon film thickness by etching, although the grain size decreases due to the columnar mode of growth at low pressures, the trap states density reduces significantly. This finding could be explained by the hypothesis that, during the growth of the material, impurities are segregated at the film surface by fast diffusion through the grain boundaries. The transport properties of 0.5- mu m-thick polysilicon films deposited at a pressure ranging from 100 to 0.5 mtorr were evaluated from measurements on thin-film transistors (TFTs). The results demonstrate that at high pressures the grain boundaries and at low pressures the polysilicon-SiO/sub 2/ interface roughness scattering are the main factors in determining the transistor performance. >

Evaluation of InP-to-silicon heterobonding

Abstract In this paper, we evaluate hydrophilic (HP) and hydrophobic (HB) surface pre-treatments in InP-to-Si direct wafer bonding. Surface roughness and surface chemistry was examined using atomic force microscopy and X-ray photoelectron spectroscopy, respectively. After bonding, the bonded interfaces were evaluated using infrared transmission imaging, bond-strength and current–voltage (I–V) measurements. It was found that HP surface treatment using oxygen plasma makes room temperature bonding of InP and Si very spontaneous, and results in high bond-strengths already after low-temperature annealing. This was not observed when using standard oxidising acids as HP surface treatment before bonding. HB InP and Si surfaces, also, did not prove to bond spontaneously at room temperature and the bond-strength started to increase only after annealing at about 400°C. HB bonding and annealing at 400°C was though the best choice regarding the electrical characteristics of the bonded InP/Si heterojunction.

Low frequency noise of GaAs Schottky diodes with embedded InAs quantum layer and self-assembled quantum dots

The electrical properties of InAs quantum layer (QL) and self-assembled quantum-dots (QDs), embedded in GaAs, are investigated by low-frequency noise measurements using Au/n-GaAs Schottky diodes as test devices. The measurements are carried out in the forward conduction regime with forward current IF as a parameter. Current–voltage and capacitance–voltage measurements indicate that GaAs and GaAs/InAs-QL Schottky diodes are nearly ideal, even though defects are present in the space–charge region of GaAs/InAs-QD Schottky diodes. In GaAs and GaAs/InAs-QL Schottky diodes, the power spectral density of the current fluctuations, S1, shows 1/f behavior and is proportional to IF2, which is explained by modulation of the barrier height due to trapping and detrapping phenomena. In GaAs/InAs-QD Schottky diodes, S1 shows 1/fγ (with γ≈0.6) behavior and is proportional to IF2 in the low current region and proportional to IF2.5 in the high current region. These noise data are explained by the generation of band tail sta...

Investigation of single electron traps induced by InAs quantum dots embedded in GaAs layer using the low-frequency noise technique

The properties of the traps induced by InAs quantum dots (QDs), embedded in a GaAs layer grown by molecular beam epitaxy, are investigated by the low-frequency noise measurements using the Au∕n-GaAs Schottky diode as a test device. The forward current noise spectra are composed of two noise components: a 1∕f-like noise at low frequencies and a generation-recombination (g-r) noise at higher frequencies. The 1∕f noise is ascribed to the mobility fluctuations within the space-charge region. The obtained Hooge parameter (αH=6×10−5) is larger than the expected value considering the phonon or impurity scattering mechanism, indicating the presence of the defects associated with QDs. The analysis of the g-r noise gives a single trap of density of about 1.6×1014cm−3 in the part of the GaAs layer located above the QDs.

Electrical transport and low frequency noise characteristics of Au/n-GaAs Schottky diodes containing InAs quantum dots

Au/n-GaAs Schottky diodes, containing layers of InAs quantum dots (QDs), are investigated by measuring the forward current–voltage characteristics in the temperature range of 77–300 K and low frequency noise at room temperature. The zero-bias barrier height decreases and the ideality factor increases with decreasing temperature, and the ideality factor was found to follow the T0-effect. The departure from the ideal thermionic-emission diffusion model was interpreted in terms of inhomogeneous Schottky contact with a Gaussian distribution of barrier heights. The excess current at small biases, observed in diodes containing layers of InAs QDs, was attributed to small patches of reduced barrier height. In the diode without QDs, the noise intensity SI shows 1/f behaviour and is proportional to I2F, which is explained by modulation of the barrier height due to trapping processes in interface states. In diodes containing InAs QDs, SI shows 1/fγ (with γ < 1) behaviour and is proportional to I2F in the high current range, which is explained by generation of band tail states with exponential energy distribution in the GaAs layer due to the QD formation. In the low current range, SI increases faster than I2F due to contribution to the noise of patches of reduced barrier height.

The effect of InAs quantum layer and quantum dots on the electrical characteristics of GaAs structures

Abstract InAs monolayer (QL) and self-aggregated quantum dots (QD) were grown by atomic layer MBE at 460°C on an n-type GaAs-buffer layer and were capped with a 2×10 16 /cm 3 n-type GaAs layer. QDs significantly reduce the capacitance measured at 1 MHz compared to samples with QL, and the capacitance and conductance of QD samples exhibit strong frequency and temperature dependence. The I – V measurements show that single QDs are laterally coupled depending on the temperature. The fast defect transients measured in the 10 ns to 1 μs range show that the charge and discharge of QDs is similar to extended defects indicating that the broad peak in capacitance DLTS spectra cannot be interpreted as isolated point defects.

Properties of CrSi2 nanocrystallites grown in a silicon matrix

Semiconducting CrSi2 nanocrystallites (NCs) were grown by reactive deposition epitaxy. The NCs were covered by 100 nm of epitaxial silicon. Their structure, morphology and optical properties were investigated by transmission electron microscopy (TEM), atomic force microscopy (AFM), ultraviolet photoelectron spectroscopy (UPS) and optical reflectance spectroscopy (ORS). The preservation of the CrSi2 phase has been justified by UPS, by ORS, and by TEM measurements. The distribution of Cr was investigated by Rutherford backscattering (RBS). The electrically active defects were investigated by deep level transient spectroscopy (DLTS). The crystal structure of the NCs nucleated near the deposition depth is identified by high-resolution TEM as hexagonal CrSi2. Energy filtered TEM shows that most of the Cr is localized in the three-dimensional (3D) NCs. RBS shows that the concentration of Cr is appropriate for the deposited quantity. In the 0.1 nm Cr sample most of the Cr is localized near the surface; in the 0.6 nm Cr sample the concentration increases at the depth of Cr deposition, while in the 1.5 nm Cr sample the excess Cr is localized near the deposition depth. DLTS Arrhenius plots give activation energies of the defects appropriate for Cr contamination, however these defects may be related to the CrSi2 NCs.

Growth and electrical characteristics of InAs/GaAs quantum well and quantum dot structures

The electrical characteristics of InAs quantum dot and quantum well structures embedded in GaAs confining layers have been compared and interpreted with the effect of the potential barrier and recharging processes of quantum dots and quantum well.

Trap centers in cuprous oxide

Abstract The effect of annealing temperature on the trap density in Cu 2 O is investigated. From space charge limited current (SCLC), Hall effect and DLTS measurements it is demonstrated that there is a trap-band distribution with the Fermi level lying within the trap-band. The maximum of this trap-band distribution is just above the Fermi level. A theoretical model is introduced to explain this trap-band distribution. Annealing of the samples in air at 400–500°C for 5 h gives the lowest total trap concentration and the lowest resistivity of the material. The above annealing decreases the total number of traps by a factor of 3 compared to the as grown samples. The resistivity decreases also by at least one order of magnitude.

SCTS:: scanning capacitance transient spectroscopy

Abstract A new working mode of scanning capacitance microscopy (SCM) is presented, extending the possibilities of the measurement from lock-in amplitude mapping to recording of capacitance transients arising as response of abrupt bias changes. Effect of Au doping in Si on SCM and scanning capacitance transient spectroscopy (SCTS) was observed. The decay time of capacitance transient, measured locally on slightly doped region shows good agreement with the conventional DLTS results.