Laurence Pierre

Formal verification of VHDL descriptions in the Prevail environment

Prevail, a formal verification environment for proving the equivalence of two very-high-speed integrated circuit hardware description language (VHDL) design architectures, is described. For simple bit-level combinational descriptions, the environment calls upon a tautology checker. For parameterized repetitive structures and for more abstract sequential designs, the program translates descriptions into recursive functions according to predefined templates and generates a theorem acceptable to the Bover-Moore theorem prover. The specification, implementation, and functional representation of a sequential example are presented.<<ETX>>

A Tractable and Fast Method for Monitoring SystemC TLM Specifications

The TLM modeling level of the systemC language emphasizes the transactions in a complex system, considered at a very high level of abstraction. This level of specification considerably improves simulation performance and is therefore increasingly being adopted. We address assertion-based verification (ABV) of TLM systemC models. We propose a framework for supervising during simulation the verification of temporal properties expressed in PSL. Very few modifications are needed in the original systemC code. The TLM specification can be timed or not. The properties can involve several channels, of different types.

ISIS: Runtime verification of TLM platforms

The context of this paper is the dynamic assertion-based verification (ABV) of TLM SystemC models. We have developed a methodology for checking temporal properties during the SystemC simulation. The assertions are expressed in the PSL language, including the possibility to use its modeling layer, and the method supports timed as well as untimed TLM descriptions. It is implemented in a prototype tool called ISIS. We describe its principles and technical characteristics, and we report various experimental results.

A formal approach to the verification of networks on chip

The current technology allows the integration on a single die of complex systems-on-chip (SoCs) that are composed of manufactured blocks (IPs), interconnected through specialized networks on chip (NoCs). IPs have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.

A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study

Networks on chip are emerging as a promising solution for the design of complex systems on a chip, to interconnect manufactured IP cores, and the need to formally guarantee their correctness is crucial. In a NoC centered design, the individual IPs are considered already validated. This paper addresses the validation of the communication infrastructure. A generic formal model for NoCs has been developed and implemented in the ACL2 theorem prover. As an application, the HERMES network has been formalized in this model, and we show that both formal proofs and simulation experiments can be performed in ACL2

A compositional model for the functional verification of high-level synthesis results

High-level synthesis systems, such as Amical, translate a behavioral description to an abstract automaton in which the states are decision and synchronization points, and operations are executed on the state transitions. After the scheduling and allocation of the functional units, the system is modeled as the interconnection of an operative and a control part. To formally verify this synthesis mechanism, we combine a detailed state encoding of the control part with an abstract view of the data part. We only compute the set of reachable states of the control part, and compose functional expressions in the data part. We show that, for each of two corresponding state transitions in the abstract automaton and in the synthesized control part, the expressions computed in the data registers and outputs are equal.

Formal semantics for PSL modeling layer and application to the verification of transactional models

The IEEE standard PSL is now a commonly accepted specification language for the Assertion-Based Verification (ABV) of complex systems. In addition to its Boolean and Temporal layers, it is syntactically extended with the Modeling layer that borrows the syntax of the HDL is which the PSL assertions are included, to manage auxiliary variables. In this paper we propose a formal, operational, semantics of PSL enriched with the Modeling layer. Moreover we describe the implementation of this notion in our tool for the dynamic ABV of SystemC TLM models. Illustrative examples are presented.

Enhancing the assertion-based verification of TLM designs with reentrancy

In this paper, we focus on the assertion-based verification (ABV) of designs described using the SystemC transactional level (TLM). Assertions are expressed in the PSL language, and the verification that the system fulfils these properties is performed dynamically i.e., during simulation. We have previously reported our results about the development of a dedicated ABV methodology that makes use of automatically generated checkers and of ad hoc observation mechanisms. The technique has also been improved to support the PSL Modeling Layer which enables the use of (global) auxiliary variables in assertions. A prototype tool, called ISIS, implements all these features. However, supporting the notion of global variables in assertions is not sufficient in general, for instance when components have a pipelined behaviour, thus enabling the simultaneous processing of several data. We propose here yet another improvement of the method, that provides for considering reentrant assertions (i.e., assertions simultaneously evaluated for different data) through the use of multiple checker instances, with local variables. We extend the PSL syntax with an appropriate syntactical construct, we adapt the semantics accordingly, and we describe the implementation in our tool. Experimental results are also reported.

High-level symbolic simulation for automatic model extraction

This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types.

Complementary Formal Approaches for Dependability Analysis

Evaluating the robustness of digital circuits with respect to soft errors has become an important part of the design flow for many applications. The identification of the most or less critical registers is often necessary, in order to reach the lowest overheads while achieving a given application-level robustness. The goal here is to identify those soft errors actually harmful for the system, not to compute the Soft Error Rate. In this context, we investigate new approaches based on formal techniques to improve design-time robustness evaluations at least for the most critical blocks in a circuit. Preliminary results are shown, focusing on the evaluation of self-healing (or self-repairing) capabilities.