Lech Jóźwiak

Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures

The functional decomposition of binary and multi-valued discrete functions and relations has been gaining more and more recognition. It has important applications in many fields of modern digital system engineering, such as combinational and sequential logic synthesis for VLSI systems, pattern analysis, knowledge discovery, machine learning, decision systems, data bases, data mining etc. However, its practical usefulness for very complex systems has been limited by the lack of an effective and efficient method for selecting the appropriate input supports for sub-systems. In this paper, a new effective and efficient functional decomposition method is proposed and discussed. This method is based on applying information relationship measures to input support selection. Using information relationship measures allows us to reduce the search space to a manageable size while retaining high-quality solutions in the reduced space. Experimental results demonstrate that the proposed method is able to construct optimal or near-optimal supports very efficiently, even for large systems. It is many times faster than the systematic support selection method, but delivers results of comparable quality.

General Decomposition and Its Use in Digital Circuit Synthesis

Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of todays complex circuits and modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.

Effective and efficient FPGA synthesis through general functional decomposition

In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom-up general functional decomposition and theory of information relationship measures that we previously developed. It differs considerably from all other known methods. The experimental results from the automatic circuit synthesis tool that implements the method clearly demonstrate that the information-driven general functional decomposition based on information relationship measures efficiently produces very fast and compact FPGA circuits.

Fast and compact sequential circuits for the FPGA-based reconfigurable systems

Reconfigurable systems fill the flexibility, performance, power dissipation, and development and fabrication cost gap between the application specifc systems implemented with hard-wired application specific integrated circuits and systems based on the standard (general purpose) programmable microprocessors. During the last decade they became the mainstream implementation technology for custom computation and embedded system products in such fields as telecommunication, image processing, video processing, multimedia, DSP, cryptography, embedded control, etc. To efficiently develop, implement and use the reconfigurable systems, adequate computer-aided support tools are necessary. Since most reconfigurable systems are implemented using the look-up table (LUT) field programmable gate arrays (FPGA) technology, the circuit synthesis tools targeting this technology are of primary importance for their effective and efficient implementation. In this paper, a new sequential circuit synthesis methodology is discussed that targets LUT FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The methodology is based on the information-driven approach to circuit synthesis, general decomposition and theory of information relationship measures that we previously developed. Our synthesis methods considerably differ from all other known methods. The experimental results from the automatic circuit synthesis tools that implement our methods demonstrate that the information-driven approach consistently applied in the whole sequential circuit synthesis chain efficiently produces very fast and compact sequential circuits.

Genetic engineering versus natural evolution: genetic algorithms with deterministic operators

Genetic algorithms (GA) have several important features that predestine them to solve design problems. Their main disadvantage however is the excessively long run-time that is needed to deliver satisfactory results for large instances of complex design problems. The main aims of this paper are (1) to demonstrate that the effective and efficient application of the GA concept to design problem solving requires substitution of the basic GAs natural evolution by genetic engineering (GE), (2) to propose and discuss the concept of a genetic engineering algorithm (GEA), and (3) to show how to apply the GEA to solve synthesis problems. In this paper, an effective and efficient GE scheme is proposed and applied to solve an important design problem: the minimal input support problem. In almost all cases, our GEA produces strictly optimal results and realizes a very good trade-off between effectiveness and efficiency. The experimental results clearly demonstrate that the proposed GE scheme is suitable for solving design problems and its application results in very effective and efficient GEAs.

An efficient for the sequential general decomposition of sequential machines

Sequential machines which derine control and serial processing units of modern digital systems are large and complex and, therefore, difficult to design, implement, optimize and verify. So, methods and CAD-tools that can decompose complex machines have attracted a great deal of interest recently. In this paper, a heuristic method is presented for suboptimal multiple-objective sequential general decomposition of sequential machines into submachines with limited input/output bits, product terms and state variables. The experimental results obtained from the prototypic implementation of the method show that the method is efficient. It produces high quality decompositions using relatively small memory and in an appropriately short time. The method is flexible and after some modifications can be applied to other decomposition problems.

Simultaneous decompositions of sequential machines

Large sequential machines are difficult to design, to optimize, to implement and to verify. Therefore, methods and CAD tools are needed that can decompose sequential machines. In this paper, we briefly describe the theoretical and practical results that were obtained in the field of simultaneous decompositions which divide the process described by a given sequential machine into a number of interacting parallel partial processes, each implemented by one partial machine.

Life-Inspired systems and their quality-driven design

The recent spectacular progress in modern microelectronics that enabled implementation of a complete complex system on a single chip created new important opportunities, but also new serious difficulties. This paper briefly analyses the situation, trends and problems in the field of the modern microelectronic-based systems. However, the main aim of the paper is to discuss the paradigms of life-inspired systems and quality-driven design that seem to be adequate to overcome the difficulties, and consider their application to the architecture synthesis for complex real-time embedded systems.

Communication and memory architecture design of application-specific high-end multiprocessors

This paper is devoted to the design of communication and memory architectures of massively parallel hardware multiprocessors necessary for the implementation of highly demanding applications. We demonstrated that for the massively parallel hardware multiprocessors the traditionally used flat communication architectures and multi-port memories do not scale well, and the memory and communication network influence on both the throughput and circuit area dominates the processors influence. To resolve the problems and ensure scalability, we proposed to design highly optimized application-specific hierarchical and/or partitioned communication and memory architectures through exploring and exploiting the regularity and hierarchy of the actual data flows of a given application. Furthermore, we proposed some data distribution and related data mapping schemes in the shared (global) partitioned memories with the aim to eliminate the memory access conflicts, as well as, to ensure that our communication design strategies will be applicable. We incorporated these architecture synthesis strategies into our quality-driven model-based multi-processor design method and related automated architecture exploration framework. Using this framework, we performed a large series of experiments that demonstrate many various important features of the synthesized memory and communication architectures. They also demonstrate that our method and related framework are able to efficiently synthesize well scalable memory and communication architectures even for the high-end multiprocessors. The gains as high as 12-times in performance and 25-times in area can be obtained when using the hierarchical communication networks instead of the flat networks. However, for the high parallelism levels only the partitioned approach ensures the scalability in performance.

Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths

Numerous applications in important domains, such as communication and multimedia, show a significant data-level parallelism (DLP). A large part of the DLP is usually exploited through application vectorization and implementation of vector operations in processors executing the applications. While the amount of DLP varies between applications of the same domain or even within a single application, processor architectures usually support a single vector width. This may not be optimal and may cause a substantial energy inefficiency. Therefore, an adequate more sophisticated exploitation of DLP is highly relevant. This paper proposes the use of heterogeneous vector widths and a method to explore the heterogeneous vector widths for VLIW ASIPs. In our context, heterogeneity corresponds to the usage of two or more different vector widths in a single ASIP. After a brief explanation of the target ASIP architecture model, the paper describes the vector-width exploration method and explains the associated design automation tools. Subsequently, experimental results are discussed.