Lennart Bamberg

High-Level Energy Estimation for Submicrometric TSV Arrays

The 3-D integration using through silicon vias (TSVs) is one of the most promising approaches to overcome the interconnect delay problem of current CMOS technologies. Nevertheless, the TSV energy consumption is not negligible due to the high capacitive coupling. This paper presents an abstract and yet accurate model to estimate the pattern-dependent energy consumption in arrays of TSVs; it is the first high-level model including the effects of the voltage-dependent metal–oxide–semiconductor (MOS) capacitances surrounding each TSV and a possible temporal misalignment between the input signals. We propose a regression method to estimate the dynamic size of the coupling capacitances as a function of the bit probabilities. Experimental results for real and synthetic data streams, a submicrometer 9-bit TSV array and a 65-nm technology show that the presented TSV energy model exhibits a maximum error of 5.53%, while the traditional high-level model shows errors of up to 79.77%. Furthermore, the new insights provided by our model reveal a possibility to easily boost the efficiency of existing low-power codes for TSV structures by over 10% without affecting the coding efficiency for the planar metal wires or the encoder complexity.

Design method for asymmetric 3D interconnect architectures with high level models

New 3D production methods enable heterogeneous integration of dies manufactured in different technology nodes. Asymmetric 3D interconnect architectures (A-3D-IAs) are the communication infrastructure targeting these heterogeneous 3D system on chips (3D SoCs), for which design methodologies and design tools are still missing. Here, a design method is proposed following an incremental approach enabled by high level models. Therefore, we present the first simulator and design framework covering the diverse requirements of A-3D-IAs. This includes an abstract model to estimate the application specific energy consumption of 2D metal wires and 3D through silicon vias (TSVs) in an A-3D-IA. It is validated by circuit simulations in combination with an electromagnetic field solver which is used for the extraction of the TSV array equivalent circuit. The model lays on a high abstraction level for fast simulations. Nonetheless, for real data stream scenarios it still shows a small maximum error of less than 8%. Additionally, a mathematical description is presented which enables a fast evaluation of low power coding schemes for A-3D-IA on a high level of abstraction.

Coding approach for low-power 3D interconnects

Through-silicon vias (TSVs) in 3D ICs show a significant power consumption, which can be reduced using coding techniques. This work presents an approach which reduces the TSV power consumption by a signal-aware bit assignment which includes inversions to exploit the MOS effect. The approach causes no overhead and results in a guaranteed reduction of the overall power consumption. An analysis of our technique shows a reduction in the TSV power consumption by up to 48 % for real correlated data streams (e.g., image sensor), and 11 % for low-power encoded random data streams.

Edge effect aware crosstalk avoidance technique for 3D integration

3D integration is one of the most promising solutions for the scaling of future integrated circuits (ICs). Nevertheless, the 2D metal wires and 3D through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs, due to their high capacitive crosstalk, which can be reduced by a coding approach. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV arrays. Additionally, these 3D CACs do not reduce the metal wire crosstalk. This work presents a crosstalk avoidance approach for 3D ICs which overcomes both limitations. The method remaps the bits of existing 2D CACs onto a TSV array in a way that results in the minimum possible TSV crosstalk. Experimental results, obtained by circuit simulations in combination with an electromagnetic field solver, show that the presented technique can reduce the crosstalk of TSVs and metal wires by about 30 % and 50 %, respectively. In comparison, with higher hardware costs, existing 3D CACs only reduce the TSV crosstalk by a maximum of 11.45 %, while providing no optimization of the metal wire crosstalk.

Energy modeling of coupled interconnects including intrinsic misalignment effects

In modern nanometric and deep sub-micron (DSM) technologies, the energy dissipation in the interconnect architecture is dominating the overall energy budget. This paper presents a precise mathematical model for the energy consumption of multi-segment interconnects, including misalignment effects. The difference in the propagation of the signals due to the unequal effective capacitance seen by each driver, produces an intrinsic misalignment that affects the power and worst-case delay in the interconnects. The notable accuracy improvement of our model leads to a better estimation of the energy consumption for each input transitions, provides a better efficiency characterization of low-power coding approaches, and can be used to study precisely stochastic approaches for interconnects. The proposed model has been experimentally validated using a commercial 65 nm technology.