Leonel Tedesco

Virtual channels in networks on chip: implementation and evaluation on hermes NoC

Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8 times 8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation

Traffic generation and performance evaluation for mesh-based NoCs

The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these methods have to address are the generation and evaluation of network traffic. Traffic generation allows injecting packets in the network according to application constraint specifications such as transmission rate and end-to-end latency. Performance evaluation helps in computing latency and throughput at network channels/interfaces, as well as to identify congestion and hot-spots. This paper reviews related works in traffic generation and performance evaluation for mesh topology NoCs, and proposes general methods for both aspects. Three parameters are used here to define traffic generation: packet spatial distribution, packet injection rate and packet size. Two types of methods to evaluate performance in NoCs are discussed: (i) external evaluation, a common strategy found in related works, where the network is considered as a black box and traffic results are obtained only from the external network interfaces; (ii) internal evaluation, where performance is computed in each network channel. The paper presents the result of experiments conducted in an 8times8 mesh network, varying the routing algorithms and the number of virtual channels. The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios

Application driven traffic modeling for NoCs

The network on chip (NoC) design process requires an adequate characterization of the application running on it to optimize communication resources utilization and dimensioning. The traffic modeling process is the most essential step for characterizing complex applications. It is possible to identify three methods to model traffic in NoC literature. The first one assumes sources continually send data at a constant rate to the network and it is the most commonly used. The second method employs probabilistic functions to model the traffic behavior for typical applications, as audio and video streams. The accuracy of this method is better, at the extra cost of modeling complexity and simulation time. The third method employs traffic traces to evaluate network performance. Even with small traces, simulation time can be prohibitive. The advantage is accuracy, superior to the previous models. Even if a given application is correctly modeled, other flows interfere on how the application traffic behaves within the network. Results about the mutual interference of different traffic flows in NoCs are scarce. This work has two main objectives: (i) compare NoC performance, in terms of throughput and latency, when different traffic models are used for the same application; (ii) evaluate the impact of network noise traffic on some specific modeled flow. Preliminary results show how far is the real NoC performance for a given application when an oversimplified model is employed. The conclusion is that NoCs must employ internal mechanisms to ensure QoS, since noise traffic makes modeled traffic to depart from its predicted behavior.

Evaluation of current QoS Mechanisms in Networks on Chip

Several propositions of NoC architectures claim to provide quality of service (QoS) guarantees, which is essential for e.g. real time and multimedia applications. The most widespread approach to attain some degree of QoS guarantee relies on a two-step process. The first step is to characterize application performance through traffic modeling and simulation. The second step consists in tuning a given network template to achieve some degree of QoS guarantee. These QoS targeted NoC templates usually provide specialized structures to allow either the creation of connections (circuit switching) or the assignment of priorities to connectionless flows. It is possible to identify three drawbacks in this approach. First, it is not possible to guarantee QoS for new applications expected to run on the system, if those are defined after the network design phase. Second, even with end-to-end delay guarantees, connectionless approaches introduce jitter. Third, to model traffic precisely for a complex application is a very hard task. The objective of this paper is to evaluate the area-performance trade-off and the limitations of circuit switching and priority scheduling to meet QoS. Preliminary results show the need of more research in this field, by considering the aggregation of more explicit techniques to control QoS

A path-load based adaptive routing algorithm for networks-on-chip

Applications executing in current MPSoCs present traffic behavior with different characteristics in terms of QoS requirements and traffic modeling. Another important MPSoC traffic feature is its unpredictability and dynamic nature. Networks-on-chip (NoCs) are communication structures being used due to higher degree of parallelism, fault tolerance, and scalability, when compared to busses. Even with increased bandwidth due to parallelism, some flows may compete for the same network resources, affecting the applications performance, and possibly violating QoS requirements. Adaptive routing algorithms may reduce such congestion, enabling dynamic path modification according to some congestion evaluation metric. State of the art approaches have a limited view of the congestion areas, since each router take routing decisions based on its neighbors congestion status. Such local decision may lead packets to another NoC congested region, therefore being inefficient. This paper proposes a new method, using the information of all routers in the source-target path. This method relies on a protocol for QoS session establishment, followed by distributed monitoring, and reroute to non-congested routers. The set of executed experiments presents results concerning latency and buffer utilization when the method proposed is applied.

Buffer sizing for QoS flows in wormhole packet switching NoCs

Networks on chip (NoCs) are communication infrastructures that offer parallelism and scalability. Most NoC designs employ wormhole packet switching, since this switching mode optimizes the use of NoC resources. However, this mode may introduce jitter, possibly producing packet loss, due to the violation of temporal QoS constraints. One technique to deal with jitter is to introduce a decoupling buffer (D-buffer) on the target IP. This buffer receives data from the NoC with jitter, while the target IP consumes data from this buffer at the application rate, without jitter. Two problems must be solved to implement D-buffers: (i) which size must the buffer have? (ii) how much buffer space should be filled before data consumption starts (threshold)? This work proposes a general method to define D-buffer size and threshold, considering the influence of packaging, arbitration, routing and concurrency between flows. Before presenting the method, the paper extends a previous traffic model for stream applications and characterizes jitter sources in wormhole packet switching. The experimental results obtained with the proposed method showed that simple traffic models employing constant frame sizes result in small D-buffers. On the other hand, employing video frames from application traces (i.e. real application data) increases buffer size and threshold, still suppressing jitter. Application traces highlight the threshold parameter importance.

A message-level monitoring protocol for QoS flows in NoCs

This work proposes a traffic monitoring scheme to be applied to NoCs. Current schemes transmit monitoring traffic to one or more MSA (Monitoring Service Access Point), and such MSAs are responsible to take some action, as task migration and fault detection. The proposed monitoring method is flow-oriented, i.e, it works at the message-level, and traffic congestion is evaluated all along the source-target path. It can be applied to different adaptation methods as adaptive routing, task migration and dynamic task mapping. Traffic information of QoS flows is stored in tables located at each router. Traffic initiators indicate the routers of the QoS flow path that should be monitored. MSAs are placed in targets of QoS traffic, and notify to the traffic source the occurrence of congestion. DATA packets are used to transmit both application data and monitoring traffic. Presented results evaluate the method in terms of area overhead, and precision/reactivity to congestion events, associated to an adaptive source routing algorithm.

Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots

Application-specific Network-on-Chip allows optimization for the interconnection to minimize its cost. When used with streaming applications, large flows of data can be predicted. However, these flows can be modified during the applications providing a dynamic flow graph. In that case, applying on off-line optimization leads to an over-sizing of the NoC. On the other hand, dynamic reconfiguration leads to unordered data deliveries with costly re-ordering units. In this paper, we propose a coarse grain dynamic reconfiguration which avoids data re-ordering requirement. We show that the proposed solution is efficient to deal with communication hot-spots, with a small area overhead, and can save up to 33% of latency.