Leslie D. Kohn
Intel
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Featured researches published by Leslie D. Kohn.
international symposium on microarchitecture | 1989
Leslie D. Kohn; Neal Margulis
The authors describe the single-chip i860 CPU, a 64-bit, RISC (reduced-instruction-set-computer)-based microprocessor that executes parallel instructions using mainframe and supercomputer architectural concepts. They designed the 1,000,000-transistor, 10-mm*15-mm processor for balanced integer, floating-point, and graphics performance. They discuss the RISC core, memory management, floating-point unit, graphics, bus interface, software support, and interfacing to a DRAM system.<<ETX>>
IEEE Computer Graphics and Applications | 1989
Jack Grimes; Leslie D. Kohn; Rajeev Bharadhwaj
A description is given of the Intel i860 processor, which was designed for use in low-cost 3D graphics workstations. These products need high performance to support the operating system, simulations, transforms, and shading calculations. The integer unit provides high performance for Unix and other operating systems, the floating-point unit provides high throughput for computationally intensive applications and the processor includes 3D graphics hardware. The sustained high computation rates are supported by on-chip caches. The processor is supported by compilers and other development tools. The i860 processor will enable cost-effective interactive scientific visualization. This includes not only the numeric computation and 3D matrix transforms but also the pixel-intensive shading calculations that normally are either very costly or very slow. Integrating all these capabilities into one component allows design of a desktop unit or a single add-in card for existing personal computers.<<ETX>>
conference on high performance computing supercomputing | 1989
Leslie D. Kohn; Neal Margulis
The Intel i860TM processor is a RISC-based microprocessor incorporating a RISC core with memory management, a floating point unit, and caches on a single chip. The 1,000,000 transistors allow a single chip implementation with highly optimized interunit communication and wide internal data buses. The parallelism and pipelining between the execution units, and the innovative cache management techniques are under explicit control of software. Vectorizable applications can use the pipelined adder and multiplier units to achieve up to 80 Mflops at 40 Mhz for the inner loops of common calculations. Special instructions allow using the data cache as a flexible vector register and support high data bandwidth from main memory. Finally, to support visualization of data, special hardware for 3D graphics is included.
national computer conference | 1982
Leslie D. Kohn
The paper discusses the benefits of microprocessor-based distributed processing systems, which are greater than those of conventional timeshared mini or main-frame systems. It highlights the advantages of the NS16000 microprocessor family for this application, and it explains how the NS16000 operating system supports distributed processing.
Archive | 1991
Leslie D. Kohn
Archive | 1992
Leslie D. Kohn
Archive | 1993
Leslie D. Kohn
Archive | 1992
Leslie D. Kohn
Archive | 1993
Leslie D. Kohn
Archive | 1992
Leslie D. Kohn