Li Du

Genetic algorithms for defect detection of flip chips

Abstract Flip chip packaging technology is widely used in high density assembly and superior performance devices. The solder joints are sandwiched between dies and substrates, leading to the defects optically opaque. Defect inspection of flip chips become more difficult. In this paper, a nondestructive detection method was presented. Ultrasonic excitations were forced on the surface of the flip chips and the raw vibration signals were measured by a laser scanning vibrometer. Eleven time domain features and twenty-four frequency domain features were extracted for analysis. After that, the genetic algorithm was introduced for feature selection and the back propagation network was adopted for classification and recognition. The flip chips were divided into three categories: good flip chips, flip chips with missing solder joints, and flip chips with open solder joints. They are recognized under the features selected by genetic algorithms rapidly and accurately, compared with those under other feature datasets, demonstrating that the approach using genetic algorithms is effective for defect inspection in flip chip packaging.

A novel bottom?up copper filling of blind silicon vias in 3D electronic packaging

Through silicon via is a promising technology that has benefits of high density, excellent performance and heterogeneous integration for 3D stacked devices, where blind silicon via plating in via first and via middle approaches is widely used. However, using conventional damascene copper plating technology to achieve high quality copper filling of blind vias is very difficult. In this paper, we demonstrate a novel approach for realizing bottom?up copper filling of blind silicon vias. Electroplating of the blind vias is carried out by using a titanium barrier layer, instead of the traditional copper seed layer, as the conductive medium. A vacuum process is introduced to push photoresist completely into the blind vias. By controlling the exposure and development processes, the photoresist at the top and middle of the vias is removed while that at the bottom it is retained for protecting the seed layer. After etching the exposed seed layer, we obtain a unique metal layer structure in which the copper seed layer is reserved at the via bottom, facilitating spontaneous bottom?up plating. Using this approach, we realize high quality copper filling of blind silicon vias of 30??m in diameter and 120??m in depth, which will be of noteworthy benefit in 3D electronic packaging.

Investigation of Fog Collection on Cactus-inspired Structures

We demonstrate the application of cactus-inspired structures for fog collection. The drop-on-cone system is modeled to analyze Gibbs free-energy gradients, equilibrium positions and motion of drops. Normalized free energy and free energy gradient are presented to characterize barrel and clam-shell drops, revealing the relations of the driving force and wettability to the half-apex angle of the cones. Small half-apex angle results in long collecting length and weak driving force. Thus it is important for fog collection to balance the driving force and collecting length with a suitable half-apex angle. Fog collection experiments on cactus-inspired structures are conducted for verification. Inflection points around 1.1° are observed, where the fog collection ability is mainly limited by the weak driving force when below the inflection points, while increases with the collecting length when above the inflection points. These indicate that the half-apex angle at the inflection point is a compromise between the driving force and collecting length, agreeing with the normalized functions. The results also prove that the hydrophilic cones are more suitable for fog collection with regard to condensation and driving force. Our research offers design guidance for efficient fog collection structure.

Using SOM neural network for X-ray inspection of missing-bump defects in three-dimensional integration

Abstract Three-dimensional integration has been a key technology in scientific research and industrial production of integrated circuits, where microbumps bridge multiple layers of chips. Microbump defect inspection, especially for missing-bump, is of major significance. We introduce self-organizing map network combined with X-ray imaging, and demonstrate a non-destructive method for rapid and effective inspection of missing microbump defects. 2D X-ray images of samples with microbumps are segmented, and vectors consisting of four features as representatives of microbumps are extracted. A self-organizing map network is constructed, and vectors of microbumps selected randomly from four samples are inputted into the network. Clusters of the defective bumps and the normal bumps are distinguished obviously. Then the other microbumps from the same samples are used for testing. The trained network can recognize the defective and normal microbumps through the clustering areas with no error. Microbumps from a different sample are inputted to the network for further verification, and high recognition accuracy is achieved. These prove the feasibility of using self-organizing map network for X-ray inspection of missing-bump defects.

Using RBF networks for detection and prediction of flip chip with missing bumps

Abstract Flip chip has been extensively used in microelectronic packaging industry. With the trend of solder bumps towards small volume and ultra-fine pitch, defect inspection of flip chips has become more difficult. In this work, we introduce radial basis function networks for detecting and predicting missing solder bumps, a typical defect in flip chips. Eight time and frequency domain features extracted from the flip chip vibration data are inputted to the networks, and flip chips with missing bumps distributed adjacently or randomly are detected and predicted. For the PAC2.1 flip chips with missing bumps distributed adjacently, we distinguish the defective flip chips from the reference one with a 100% accuracy. The flip chips with 1 to 2 missing solder bumps are then trained and detected accurately by the network, and the chip with 3 missing bumps can be predicted exactly as well. After that, we train the network with the data of flip chips with 1 to 4 missing bumps. The network can recognize the number of the missing bumps in these flip chips with a 100% accuracy, and predict 5 missing bumps in the flip chip with the accuracy of 91.7%. For further validation, we use the PB08 flip chips with missing bumps distributed adjacently or randomly for training, testing and prediction, and also obtain high accuracies. These prove the feasibility of using RBF networks for detection and prediction of flip chips with missing bumps in engineering.

Reliable Cu-Cu Thermocompression Bonding by Low Temperature Sintered Cu Nanowires

Cu-Cu thermocompression bonding is the most widely accepted bonding approach for realizing multilayer chip stacking in three dimensional integrated circuits. Recently new materials and structures such as one-dimensional metallic nanostructures have been extensively investigated for the application of Cu-Cu interconnection due to their superior electrical, thermal, and mechanical properties. Herein, we presented a reliable Cu-Cu thermocompression bonding approach using low temperature sintered Cu nanowires. Large-scale Cu nanowires with the diameter of 50 nm–100 nm were fabricated on a silicon substrate via a direct thermal decomposition-reduction process. A simple solution-immersion step was first utilized to synthesize Cu(OH)2 nanowires on a silicon substrate covered with an electroplated Cu film. Subsequently a decomposition process was conducted at 200 °C for 3 h in an Ar atmosphere, followed by a reduction process conducted at 300 °C for 3 h in a 10% H2/Ar atmosphere to completely convert Cu(OH)2 to Cu nanowires. Sintering of the Cu nanowires was observed to occur at a low temperature of 350 °C in a 10% H2/Ar atmosphere. Then Cu-Cu thermocompression bonding using the low temperature sintered Cu nanowires was performed at 300 °C for 60 min in the H2/Ar reductive atmosphere, where densely connected bonding interface was obtained. Our study provided a promising solution to obtain reliable Cu-Cu bonding using Cu nanowires for future three-dimensional integrated circuits.

Low Temperature Cu Nanorod/Sn/Cu Nanorod Bonding Technology for 3D Integration

Three-dimensional integration is an emerging and promising architecture for system-level integration towards higher performance, smaller form factor, lower cost and more functionality. In this paper, a novel low temperature Cu nanorod/Sn/Cu nanorod solid-state-diffusion bonding approach for 3D integration was proposed and investigated. Cu nanorods were deposited on the electroplated Cu surface by an oblique angle deposition technique, and a Sn film was deposited on the Cu nanorod layer in sequence. Samples with electroplated Cu/Sn films were also prepared for comparison. The morphology evolutions of the Cu nanorod/Sn and Cu/Sn structures after reflowed from room temperature to 200°C were studied. The Cu nanorod/Sn structure exhibited a higher coalescent rate compared with the Cu/Sn structure because of the high surface energy of Cu nanorod, which may promote the solid state diffusion and reaction of Cu and Sn atoms during the thermo-compression process. The samples with Cu nanorod/Sn structures were then bonded face-to-face at temperatures below the melting point of Sn with an external pressure. The bonding duration was 20 minutes. The SEM results showed that the Cu nanorod/Sn layers on both samples fused together successfully and intermetallic compounds were formed at a bonding temperature as low as 100°C. When increasing the bonding temperature to 200°C, we obtained a denser bonding interface accompanying with further growth of intermetallic compounds. Our study demonstrated the feasibility of using Cu nanorod/Sn/Cu nanorod solid-state-diffusion for low temperature wafer bonding.

Defect inspection of copper bonding using ultrasound

Three dimensional packaging based on TSV is considered to be promising and has been accepted as the next generation technology for packaging. There are many advantages such as high speed interconnection, ultrafine pitch and high density integration. Copper bonding is one of the key bonding technologies to achieve 3D packaging with fine electrical interconnection, excellent path for thermal transfer and high mechanical reliability. The bonding interfaces are sandwiched between two wafers, leading to the defect optically opaque. Defect inspection of copper bonding becomes more difficult. In this paper, a nondestructive detection method was presented. We used 230 MHz ultrasonic transducer for copper bonding testing and captured the reflected time domain signals when the transducer scanning the copper bonding chips. The bonding layer was located in the time domain signals and the images of the bonding samples were generated by scanning acoustic microscopy. Due to the ability to deal with small sample data, the support vector machine was adopted to process the bonding images. Only ten pixel points of good bonding interface and ten pixel points of bonding interface with voids were captured to train the support vector machine, and then the whole bonding image was tested by the trained support vector machine. Meanwhile, the simple binary method with default threshold was used for the bonding image processing. The cross-section view was prepared in an epoxy mount and polished. Scanning electron microscopy analysis validated the detection results. The approach using the support vector machine shows better processing results and robustness compared to the simple binary method. Therefore, the method using ultrasound for defect inspection is effective in copper bonding.