Lili He

The design of a low-power low-noise phase lock loop

A phase lock loop is a closed-loop system that causes one system to track with another. More precisely, a PLL can be perceived as a circuit synchronizing an output signal with a reference or input signal in frequency as well as phase. High-performance phase lock loops are widely used within a digital system for clock generation, timing recovery, and to efficiently sequence operations and synchronize between function units and ICs As the digital system grows the role of phase lock loop increases. Achieving low jitter and phase noise in phase lock loop with less area and power consumption is challenging. The present research relates to characterization and redesign of individual blocks of Phase lock loop (PLL) to improve its characteristics. More specifically redesigning of individual blocks like: Phase Frequency Detector to reduce area and static phase error, Voltage to Current converter to linearly increase the current input to the current controlled oscillator, Current Controlled Oscillator to reduce phase noise, amplitude distortion, area and power consumption. We also introduce an additional feedback loop to increase the gain of the charge pump in a manner that linearizes the overall loop gain over wide bandwidth. The Results are substantial improvements in the PLL characteristics such as low jitter, phase noise, area and power consumption.

An innovative solar system with high efficiency and low cost

We present an innovative high efficiency, low cost solar system that can be easily adapted for commercial applications. The solar system separates the wavelengths and concentrates the different wavelengths using one inexpensive Fresnel lens. This allows the specific solar cells to have concentrated light for a specific region of the spectrum which allows for the solar cell to be optimized for that region of the spectrum.

Clock and data recovery for a 6 Gbps SerDes receiver

This paper presents the design and implementation of a 6 Gbps clock and data recovery (CDR) system for Serial Advanced Technology Attachment (SATA) standard. The CDR incorporates half rate phase detector and is realized using a 2 loop PLL consisting of a coarse loop and a fine loop. Fast frequency acquisition is acquired through coarse loop and fine phase alignment is performed through a half rate fine loop. While the coarse loop can recover clock ranging from 2.5 GHz to 3.2 GHz the fine loop has an acquisition range of 200 KHz. The design has been implemented in IBM 0.13um CMOS technology. Verilog AMS and Matlab were used for front end design and Cadence for schematic and layout implementation. The overall silicon area of the CDR is approximately 108 X 244 um2 excluding loop filter capacitors.

First-Order Continuous-Time Sigma-Delta Modulator

This paper presents the design of a first-order continuous-time sigma-delta modulator. It can accept input signal bandwidth of 10 kHz with oversampling ratio of 250. The modulator operates at 1.8 V supply voltage and uses 0.18 mum CMOS technology. It achieves a level of 60 dB SNR

Capacitor free phase locked loop design in 45nm

The paper describes the design of a capacitor-free phased locked loop realized using 45 nm technology. Phase locked loops (PLL) find widespread application in electronic circuits, especially in generating high speed clocks for digital chips. Traditional analog PLL designs use capacitors and resistors in the charge pump and the filter circuits. These components occupy large area, adding to the circuit cost; in addition to consuming more power. These limitations can be removed by building a completely digital PLL. But fully digital PLLs have their own drawbacks, especially inaccuracies due to the quantization errors, coarser-grain control of the output frequency generation and errors at higher frequencies. As a result, completely digital PLLs are not suited for generating high frequency signals. In this paper, we present the design of a capacitor-free PLL. It retains the analog Voltage Controlled Oscillator (VCO) in order to run accurately at high frequencies, but replaces all other analog components with their digital counterparts. Incorporation of the digital components eliminates the capacitors and resistors in the circuit and reduces the circuit area and power consumption, while also making the design independent of thermal noise, aging, mismatch and leakage due to the charge pump.

Implementation of power managed hyper transport system for transmission of HD video

Hyper transport is a bidirectional, serial/parallel high bandwidth, low latency, point-to-point interface architecture. In this architecture, data can be sent on both rising and falling edges of the clock making it an interface that can transmit the data faster when compared to the other architectures that are available in the market today. This architecture also is ACPI (Advanced Configuration and Power Interface) compliant and can provide low power by switching off when there is no activity in the system. This project is aimed to develop a power managed Hyper Transport system prototype for the transmission of High Definition video. Power is managed by switching the system from active state to sleep state when there is no heavy isochronous data flowing and switching it back to the active state before isochronous data arrives, while by-passing the prioritized video data and interrupts. This project is implemented in Verilog and is simulated using ModelSim. From the simulations, it can be observed that at 50%¿70% of isochronous data transfer an overall power saving of 20% ¿ 40% is achieved.

CMOS Based Low Cost Temperature Sensor

This paper presents the design of low power, low cost design of temperature sensor that has been designed keeping in view VLSI circuits and technology changes. The circuit occupies an area close to 0.01 mm , which is less than 1/100th of the area occupied by most of the previous circuits that use capacitors and A/D converters. Power dissipation of the circuit ranges from 800 muW to 1.2 mW for temperatures ranging between -20degC to 80degC. It has been implemented using TSMC 0.18 mum technology.

Phase Aligned Clock Multiplier

Phase aligned clock multiplier is designed for high performance applications where high-speed clocks are needed including PCs, workstations, and telecom applications. In this paper, a clock multiplier is designed based on the ideology of phase locked loops. It has the following features: operating supply voltage is 1.8 V ; input frequency range is 10-83.33 MHz; output frequency range is 5-166.67 MHz ; input-to-output skew is 200 ps ; 3-multiplier configuration ; output selectable pin phase alignment; single phase locked loop architecture; internal loop filter.

A 8b 10Ms/s Low Power Pipelined A/D Converter

This paper describes an 8-bit, 10 MSamples/second analog to digital converter, with 2V fully differential input range, which is implemented in TSMC 0.25mum CMOS technology. It achieves low power dissipation of 25mW, and the chip area is 0.56mm2. Measured performance yields a very good VTC curve and a sine wave fitting curve for 200KHz input at 10Msample/s, DNL testing of -0.2LSB-0.75LSB; INL testing of -0.2LSB ~ 0.65LSB, 44.62dB of SNDR (signal to noise plus distortion ratio) and ENOB of 7.12 bits

A low input, low-power dissipation CMOS ADC

This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology