Lin Fujiang

A 0.18 μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

This paper presents an inductorless complementary-noise-canceling LNA (CNCLNA) for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5–16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best P1dB is −7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2 × 0.2 mm2.

A digitally controlled power amplifier with neutralization capacitors for Zigbee™ applications

This paper presents a single chip CMOS power amplifier with neutralization capacitors for Zigbee™ system according to IEEE 802.15.4. A novel structure with digital interface is adopted, which allows the output power of a PA to be controlled by baseband signal directly, so there is no need for DAC. The neutralization capacitors will increase reverse isolation. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed power amplifier has a 13.5 dB power gain, 3.48 dBm output power and 35.1% PAE at P1dB point. The core area is 0.73 × 0.55 mm2.

An efficient digital calibration technique for timing mismatch in time-interleaved ADCs

An efficient digital calibration technique for timing mismatch in time-interleaved ADCs is presented. It depends on the phase detection between a reference clock and the sampling clock of each sub-ADC in TIADC system. A method of variable delay line is used to compensate the timing mismatch. The mismatch detection and compensation form a feedback loop and can achieve a real-time tracking and correcting. Simulation results showed that this technique can have the timing mismatch calibrated quickly and correctly within the entire Nyquist sampling frequency by the virtue of a smaller hardware, and can be applied to any number of TIADC.

A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm2.

Design optimizations of phase noise, power consumption and frequency tuning for VCO

To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise, power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and up-conversion of flicker noise from cross-coupled pair are reduced by improved self-switched biasing technology, leading to low close-in phase noise. Low power is achieved by low supply voltage and triode region biasing. To linearly tune the frequency and get constant gain, distributed varactor structure is adopted. The proposed VCO is fabricated in SMIC 0.18-μm CMOS process. The measured linear tuning range is from 2.38 to 2.61 GHz. The oscillator exhibits low phase noise of −77.5 dBc/Hz and −122.8 dBc/Hz at 10 kHz and 1 MHz offset, respectively, at 2.55 GHz oscillation frequency while dissipating 2.7 mA from 1.2 V supply voltage, which well meet design specifications.

A tri-mode high light-load efficiency BUCK converter for mobile phone application

This paper proposes a wide output range and tri-mode BUCK circuit which utilizes PWM mode, PFM mode and PSM mode at heavy, light and very light loads respectively. By shutting down the majority of the internal modules, employing minimum loop control and reducing the quiescent current, the design could lower the static power consumption. The work, therefore, could increase efficiency at very light load. The proposed BUCK is fabricated using SMIC 0.18 μm process. Test results show that when the input is 4V and the output is 1.8V, the efficiency of the proposed BUCK is 90% and 85% at 300mA and 5mA load current respectively.

A 0.18 μm CMOS Gilbert low noise mixer with noise cancellation

This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz. The Gilbert mixer is known for its perfect port isolation and bad noise performance. The noise cancellation technique of LNA can be applied here to have a better NF. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed low noise mixer has a 13.7–19.5 dB voltage gain from 10 MHz to 0.9 GHz, an average noise figure of 5 dB and a minimum value of 4.3 dB. The core area is 0.6 × 0.45 mm2.

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process*

This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm 2 .

A low-power time-domain VCO-based ADC in 65 nm CMOS

A low-power, high-FoM (figure of merit), time-domain VCO (voltage controlled oscillator)-based ADC (analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator (ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic- distortion-cancellation technique to its transconductance stage, which increases the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCOs V-F(voltage to frequency)conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADCs low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.

A 3–5 GHz BPSK transmitter for IR-UWB in 0.18 μm CMOS

This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system. It is based on up-conversion with a high linearity passive mixer. Unlike the traditional BPSK modulation scheme, the local oscillator (LO) is modulated by the baseband data instead of the pulse. The chip is designed and fabricated by standard 0.18 ?m CMOS technology. The transmitter achieves a high data rate up to 400 Mbps. The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier. The maximum peak-to-peak amplitude of the pulse is 600 mV. It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate. The energy efficiency is 91.4 pJ/pulse. The die area is 1.4 ? 1.4 mm2.