Linda S. DeBrunner

Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic

Distributed arithmetic (DA) is performed to design bit-level architectures for vector-vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. In this brief, two novel DA-based implementation schemes are proposed for adaptive finite-impulse response filters. Different from conventional DA techniques, our proposed schemes use coefficients as addresses to access a series of lookup tables (LUTs) storing sums of delayed and scaled input samples. Two smart LUT updating methods are developed, and least-mean-square adaptation is performed to update the weights and minimize the mean square error between the estimated and desired output. Results show that our two high-performance designs achieve high speed, low computation complexities, and low area cost.

On the Design of Sparse Half-Band Like FIR Filters

In this work we consider the design of sparse FIR filters, i.e. filters with few non-zero multiplications. The considered filters have half-band like properties, but with slightly relaxed specifications compared with actual half-band filters. We propose a filter design technique where the number of non-zero filter coefficients is minimized. It is shown by examples that it is possible to take advantage of an increased passband ripple only to obtain a half-band like solution with fewer non-zero multiplications. Decreasing the passband edge only does not give such a direct improvement.

Error control and concealment for image transmission

In the practical transmission of compressed still images, bit errors may occur, which probably result in desynchronization and packet loss. In packet-switched networks, network congestion also results in packet loss. This survey article reviews the error resilience factors that must be faced by a robust image encoder and decoder (codec). The article begins with the enumeration of the different kinds of impact noisy channels and congested networks have on block-coded images. Then we present different techniques that can be applied to combat the degradation of the images introduced by the noisy channel and network congestion. These techniques include resynchronization strategies, post-processing error concealment algorithms, and preprocessing error control techniques. All these techniques can be either used directly or extended to robust video transmission.

An efficient design for FIR filters with variable precision

We present an improved algorithm for selecting variable precision coefficients for FIR filters that produces a reduced space implementation with no degradation in frequency response. The algorithm is based on the fact that the frequency response of a filter has different sensitivities to different coefficients depending on the response itself (i.e. the coefficient value). The method provided here makes it possible to predict the variable precision of the quantized coefficients that are required to meet the specification. This approach, along with other technologies such as CSD and the scaling method used in our realizations, has opened exciting implementation possibilities for FPGAs, ASICs, and custom VLSI. The example study in this paper shows that using variable precision to exploit redundancy across the coefficients results in significant reductions in complexity and area over the uniform wordlength method.

Minimum adder depth multiple constant multiplication algorithm for low power FIR filters

In this work we propose a graph based minimum adder depth algorithm for the multiple constant multiplication (MCM) problem. Hence, all multiplier coefficients are here guaranteed to be realized at the theoretically lowest depth possible. The motivation for low adder depth is that this has been shown to be a main factor for the power consumption. An FIR filter is implemented using different MCM algorithms, and the proposed algorithm result in 25% lower power in the MCM part compared to algorithms focused on minimizing the number of adders.

A novel adaptive filter implementation scheme using distributed arithmetic

Distributed arithmetic (DA) is performed to design bit-level architectures for vector-vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. In this work, a DA based FIR adaptive filter implementation scheme is proposed. Different from existing DA schemes, our proposed scheme uses coefficients as addresses to access a series of look-up tables (LUTs) storing sums of delayed and scaled input samples. With least mean square (LMS) adaptation, offset-binary coding (OBC) based LUT updating method is presented as well. Results show that our high performance design achieves high-speed, low computation complexity, and low area cost.

Sub-band adaptive filtering with delay compensation for active control

This paper introduces a filtered-x least-mean-square (FXLMS) based sub-band adaptive algorithm with error path delay compensation. Our algorithm avoids the signal path delay while compensating for the error path delay, thus increasing system stability. Simulation results are presented to demonstrate experimentally the efficiency of this new adaptive algorithm.

Sparse FIR filters and the impact on FPGA area usage

In FIR filter design, a sparse filter is one that has a majority of zeros for coefficients. Generally, a sparse filter is designed in order to save area and speed up computations, but when implementing a sparse filter in an FPGA the expected area savings may not be realized. This paper shows that sparsity in an FIR filter does not generally translate directly into FPGA space (area) savings on a Virtex-4 FPGA.

Variable wordlength IIR filter implementations for reduced space designs

This paper presents our work in minimizing the required space on a field programmable gate array (FPGA) for IIR digital filters. The method does not alter the filter frequency response. The assumption is that the reduced space design will naturally reduce power consumption, as well. We have used distributed look-up tables in a Xilinx XC4000 FPGA to implement our multiplications. The basis of our method is that variable wordlengths can be implemented throughout the design to reduce space without increasing output quantization noise power. Our method will work on any IIR filter type and structure, and can be used either during the design process or after the design has been completed. Our example shows that a 15%-20% reduction in space for equivalent performance is possible. One other important result of our work is that filter order alone is an inadequate measure of complexity.

FPGA model of a high-frequency power electronic converter in an RTDS power system co-simulation

This paper presents the work being done in developing Field Programmable Gate Array (FPGA) based high-frequency power electronic models in co-simulation with Real Time Digital Simulator (RTDS) small time step models. With the inclusion of FPGAs in the Electromagnetic Transient simulations, higher frequencies for power electronic models, which were not previously possible using only RTDS, can be achieved. A two port buck converter is modeled on an FPGA using Dommels algorithm and interfaced with the small time-step environment in RTDS using a travelling wave model. The RTDS small time-step size is 2 μs, whereas the time-step for the FPGA is 300 ns. This paper presents the results and challenges faced in developing this system.