Lisa M. Porter

High-carbon concentrations at the silicon dioxide–silicon carbide interface identified by electron energy loss spectroscopy

High carbon concentrations at distinct regions at thermally-grown SiO2/6H-SiC(0001) interfaces have been detected by electron energy loss spectroscopy (EELS). The thickness of these C-rich regions is estimated to be 10-15 Angstrom. The oxides were grown on n-type 6H-SiC at 1100 degrees C in a wet O-2 ambient for 4 h immediately after cleaning the substrates with the complete RCA process. In contrast, C-rich regions were not detected from EELS analyses of thermally grown SiO2/Si interfaces nor of chemical vapor deposition deposited SiO2/SiC interfaces. Silicon-rich layers within the SiC substrate adjacent to the thermally grown SiO2/SiC interface were also evident. The interface state density D-it in metal-oxide-SiC diodes (with thermally grown SiO2) was approximately 9x10(11) cm(-2) eV(-1) at E- E-v=2.0 eV, which compares well with reported values for SiC metal-oxide-semiconductor (MOS) diodes that have not received a postoxidation anneal. The C-rich regions and the change in SiC stoichiometry may be associated with the higher than desirable D-its and the low channel mobilities in SiC-based MOS field effect transistors

Inhomogeneities in Ni/4H-SiC Schottky barriers: Localized Fermi-level pinning by defect states

We investigated arrays of Ni, Pt, or Ti Schottky diodes on n-type 4H-SiC epitaxial layers using current-voltage (I-V) measurements, electron beam induced current (EBIC), polarized light microscopy, x-ray topography, and depth-resolved cathodoluminescence spectroscopy. A significant percentage of diodes (∼7%–30% depending on epitaxial growth method and diode size) displayed “nonideal” or inhomogeneous barrier height characteristics. We used a thermionic emission model based on two parallel diodes to determine the barrier heights and ideality factors of high- and low-barrier regions within individual nonideal diodes. Whereas high-barrier barrier heights increased with metal work function, low-barrier barrier heights remained constant at ∼0.60, 0.85, and 1.05eV. The sources of these nonidealities were investigated with a variety of spectroscopic and imaging techniques to determine the nature and energy levels of the defects. EBIC indicated that clusters of defects occurred in all inhomogeneous diodes. Cathod...

Observation of a Non-stoichiometric Layer at the Silicon Dioxide – Silicon Carbide Interface: Effect of Oxidation Temperature and Post-Oxidation Processing Conditions

Thermal oxides were grown on n-type 6H-SiC(0001) at 1100 °C for 2 hrs in a wet oxygen ambient after the substrates were cleaned using the complete RCA cleaning process. Metal-oxide-semiconductor (MOS) diodes were then fabricated and subsequently cleaned under different annealing conditions, including re-oxidation-, NO-, and forming gas (10% H 2 + 90% N 2 )-annealing at 950 °C for one hour. Measurements of the interface state densities (D it ) at room temperature showed that post oxidation annealing (POA) reduced the D it values to a varying degree depending on the specific annealing condition. Annealing in NO and forming gas resulted in the largest reduction in D it values. Oxides were grown at 950, 1100, and 1250 °C for varying amounts of time without receiving POA. A non-stoichiometric (Si x C, x>1) transition layer adjacent to the SiO 2 /SiC interface has been observed by electron energy loss spectroscopy (EELS). The thickness of this layer was found to increase with oxidation temperature and was not observed at all for a thin oxide grown at 950 °C. The D it values (close to the conduction band) for diodes with oxides grown at 950°C without POA were lower than the D it values for the samples oxidized at 1100 °C with any of the POA treatments. While the thickness of the transition layer was found to be dependent on temperature, our results indicate that it is independent of oxide thickness. This transition layer may be associated with the high D it values and low channel mobilities for SiC MOSFETs.

Electrical, structural, and chemical analysis of silicon carbide-based metal-oxide-semiconductor field-effect-transistors

In this study we investigated the morphology and interfacial chemistry of (0001) 4H-SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) as a function of post-oxidation annealing in nitric oxide (NO) following wet oxidation. Energy-filtered transmission electron microscopy analyses showed enhanced C/Si concentrations (up to 13%) at distinct locations along the SiO2/SiC interface in the MOSFETs that were not annealed in NO. In contrast, regions of enhanced C/Si concentration were not detected in the MOSFETs that were annealed in NO; instead, these samples showed a trace amount of interfacial N. The introduction of N may therefore be associated with a reduction of C in these samples and may contribute to the higher channel mobility (∼38 cm2/V s) in the samples annealed in NO relative to the samples that were not annealed in NO (∼9 cm2/V s). Rough SiO2/4H-SiC interfaces and nonuniform oxide thickness were observed on both the NO- and the non-NO-annealed samples. The rough interfaces shown i...

Defect-driven inhomogeneities in Ni∕4H–SiC Schottky barriers

Nanoscale depth-resolved cathodoluminescence spectroscopy (DRCLS) of Ni diode arrays on 4H-SiC epitaxial wafers reveals a striking correspondence between deep level defects and electrical transport measurements on a diode-by-diode basis. Current-voltage measurements display both ideal and nonideal diode characteristics due to multiple barriers within individual contacts. Near-interface DRCLS demonstrates the presence of three discrete midgap defect levels with 2.2, 2.45, and 2.65eV emission energies whose concentrations vary on a submicron scale among and within individual diodes, correlating with barrier inhomogeneity. These results also suggest that SiC native defect levels can account for the maximum range of n-type barrier heights.

Si/SiO2 and SiC/SiO2 Interfaces for MOSFETs – Challenges and Advances

Silicon has been the semiconductor of choice for microelectronics largely because of the unique properties of its native oxide (SiO2) and the Si/SiO2 interface. For high-temperature and/or high-power applications, however, one needs a semiconductor with a wider energy gap and higher thermal conductivity. Silicon carbide has the right properties and the same native oxide as Si. However, in the late 1990’s it was found that the SiC/SiO2 interface had high interface trap densities, resulting in poor electron mobilities. Annealing in hydrogen, which is key to the quality of Si/SiO2 interfaces, proved ineffective. This paper presents a synthesis of theoretical and experimental work by the authors in the last six years and parallel work in the literature. High-quality SiC/SiO2 interfaces were achieved by annealing in NO gas and monatomic H. The key elements that lead to highquality Si/SiO2 interfaces and low-quality SiC/SiO2 interfaces are identified and the role of N and H treatments is described. More specifically, optimal Si and SiC surfaces for oxidation are identified and the atomic-scale processes of oxidation and resulting interface defects are described. In the case of SiC, we conclude that excess carbon at the SiC/SiO2 interface leads to a bonded Si-C-O interlayer with a mix of fourfold- and threefold-coordinated C and Si atoms. The threefold coordinated atoms are responsible for the high interface trap density and can be eliminated either by H-passivation or replacement by N. Residual Si-Si bonds, which are partially passivated by H and N remain the main limitation. Perspectives for the future for both Si- and SiC-based MOSFETs are discussed.

Tantalum carbide ohmic contacts to n-type silicon carbide

Tantalum carbide contacts with and without Au, Pt, and W/WC overlayers on n-type 6H–SiC (0001) were ohmic after annealing at temperatures between 800 and 1075 °C. Specific contact resistivities (SCRs) were calculated from current–voltage measurements of transmission line model patterns at temperatures ranging from 20 to 400 °C in air. The minimum SCRs at room temperature on SiC (2.3×1019 cm−3) for TaC and for TaC with Pt and Au overlayers were 2.1×10−5, 7.4×10−6, and 1.4×10−6 Ω cm2, respectively. The SCRs for both the Au/TaC/SiC (5.3×10−7Ω cm2) and the Pt/TaC/SiC (7.5×10−7 Ω cm2) samples decreased with measurement temperature to 200 and 400 °C, respectively, while the latter samples showed reversibility after heating to 400 °C. W/WC/TaC/SiC samples showed the best stability after annealing at 400 °C for 144 h in vacuum. Changes in the electrical characteristics were correlated with increases in O incorporation in the contacts as a result of annealing. Investigation of the TaC/SiC interface by transmission...

Layer-by-layer thermal conductivities of the Group III nitride films in blue/green light emitting diodes

Thermal conductivities (k) of the individual layers of a GaN-based light emitting diode (LED) were measured along [0001] using the 3-omega method from 100-400 K. Base layers of AlN, GaN, and InGaN, grown by organometallic vapor phase epitaxy on SiC, have effective k much lower than bulk values. The 100 nm thick AlN layer has k = 0.93 ± 0.16 W/mK at 300 K, which is suppressed >100 times relative to bulk AlN. Transmission electron microscope images revealed high dislocation densities (4 × 1010 cm−2) within AlN and a severely defective AlN-SiC interface that cause additional phonon scattering. Resultant thermal resistances degrade LED performance and lifetime making layer-by-layer k, a critical design metric for LEDs.

Nitridation anisotropy in SiO2∕4H–SiC

Nitrogen incorporation at the SiO2∕SiC interface due to annealing in NO is measured and shown to be a strong function of crystal face. The annealing process involves two major solid-state chemical reactions: nitrogen uptake at the interface and N loss associated with second-order oxidation. An ad hoc kinetics model explains the experimental observations of anisotropy and nitrogen saturation.

Effect of self-assembled monolayers on charge injection and transport in poly(3-hexylthiophene)-based field-effect transistors at different channel length scales.

Charge injection and transport in bottom-contact regioregular-poly(3-hexylthiophene) (rr-P3HT) based field-effect transistors (FETs), wherein the Au source and drain contacts are modified by self-assembled monolayers (SAMs), is reported at different channel length scales. Ultraviolet photoelectron spectroscopy is used to measure the change in metal work function upon treatment with four SAMs consisting of thiol-adsorbates of different chemical composition. Treatment of FETs with electron-poor (electron-rich) SAMs resulted in an increase (decrease) in contact metal work function because of the electron-withdrawing (-donating) tendency of the polar molecules. The change in metal work function affects charge injection and is reflected in the form of the modulation of the contact resistance, R(C). For example, R(C) decreased to 0.18 MΩ in the case of the (electron-poor) 3,5-bis-trifluoromethylbenzenethiol treated contacts from the value of 0.61 MΩ measured in the case of clean Au-contacts, whereas it increased to 0.97 MΩ in the case of the (electron-rich) 3-thiomethylthiophene treated contacts. Field-effect mobility values are observed to be affected in short-channel devices (<20 μm) but not in long-channel devices. This channel-length-dependent behavior of mobility is attributed to grain-boundary limited charge transport at longer channel lengths in these devices.