Liu Zhongli

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

A 10-bit 50-MS/s reference-fee low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC (CDAC) is implemented to cancel the offset of the latch-type sense amplifier (SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit (FOM) of 61.1 fJ/conversion-step.

Total dose radiation response of modified commercial silicon-on-insulator materials with nitrogen implanted buried oxide

Nitrogen ions of various doses are implanted into the buried oxide (BOX) of commercial silicon-on-insulator (SOI) materials, and subsequent annealings are carried out at various temperatures. The total dose radiation responses of the nitrogen-implanted SOI wafers are characterized by the high frequency capacitance-voltage (C—V) technique after irradiation using a Co-60 source. It is found that there exist relatively complex relationships between the radiation hardness of the nitrogen implanted BOX and the nitrogen implantation dose at different irradiation doses. The experimental results also suggest that a lower dose nitrogen implantation and a higher post-implantation annealing temperature are suitable for improving the radiation hardness of SOI wafer. Based on the measured C—V data, secondary ion mass spectrometry (SIMS), and Fourier transform infrared (FTIR) spectroscopy, the total dose responses of the nitrogen-implanted SOI wafers are discussed.

Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance–voltage (C–V) analysis.

Silicon-on-Insulator Based 2×2 Multimode Interference Coupler with Large Tolerance

We demonstrate a type of 2 x 2 multimode interference 3 dB coupler based on silicon-on-insulator. The fabrication tolerance was investigated by the effective index method and the guide mode method. The devices with different lengths were fabricated and near-held output images were obtained. Tolerances to width, length and etch depth are 2, 200 and 2 mum, respectively. The devices show a uniform power distribution.

Radiation Hardened 128K PDSOI CMOS Static RAM

A fast 128K-bit asynchronous SRAM with access time of 25 ns is presented. It used a radiation hardened 0.8-micron CMOS/SOI process with 3 layers of metal. It features 500 muA stand-by current, 20mA@10MHz operating current, 500K rad(Si) total dose tolerant and 2.45times10 11rad (Si)/s dose rate survivability. The circuit operates with ambient temperature from -25 to +125degC and power supply from 4.5 to 5.5V. A 28-pin dual-in-line flat pack package is used

Effects of Techniques of Implanting Nitrogen into Buried Oxide on the Characteristics of Partially Depleted SOI PMOSFET

Effects of techniques of implanting nitrogen into buried oxide on the characteristics of the partially depleted silicon-on-insulator (SOI) p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) have been studied with three different nitrogen implantation doses, 8 x 10(15), 2 x 10(16), and 1 x 10(17) cm(-2). The experimental results show that this technology can affect the threshold voltage, channel hole mobility and output characteristics of the partially depleted SOI PMOSFETs fabricated with the given material and process. For each type of the partially depleted SOI PMOSFET with nitrided buried oxide, the absolute value of the average threshold voltage increases due to the nitrogen implantation. At the same time, the average channel hole mobility decreases because of the nitrogen implantation. In particular, with the high nitrogen implantation doses, the output characteristic curves of the tested transistors present a distinct kink effect, which normally exists in the characteristic output curves of only partially depleted SOI NMOSFETs.

An Low-Power 128Kb SRAM with 0.2um FDSOI and its TID radiation response

A 128K-bit Low-Power SRAM with 0.2um Fully-Depleted(FD) SOI CMOS process is presented. First-cut datalO and Busr-Splitting techniques are used in the SRAM circuit design to achieve 15uA standby mode current and 20uA~500uA active mode current after packaged in DIP28. The SRAMs Total-lonizing-Dose capability is about 20K rad(Si).

Dependence of ultra-thin gate oxide reliability on surface cleaning approach

In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H/sub 2/SO/sub 4//H/sub 2/O/sub 2/(SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.

JFET/SOS devices: processing and gamma radiation effects

A process for fabricating n-channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p/sup +/-n junction was obtained by diffusion, and the conductive channel formed by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co/sub 60/ /spl gamma/-ray irradiation experiments, we found that the devices had a good total dose radiation hardness. When the total dose was 5 Mrad(Si), their threshold voltages shift was less than 0.1 V. The variation of transconductance and the channel leakage current were also small.