Lixia Zheng

A hybrid time-to-digital converter based on residual time extraction and amplification

This paper presents a novel hybrid time-to-digital converter (TDC) for high resolution and wide range time measurement, where a two-stage TDC cooperates with a two-step TDC. First the input time is roughly converted by a coarse-fine two-stage TDC to guarantee wide dynamic range and small quantization error. Then the residual time from the previous conversion is obtained by an extraction circuit and further quantified by a two-step TDC for ultra fine resolution, where the extracted residue is linearly enlarged by a time amplifier (TA), followed by adopting a tapped delay line with original gate delay resolution for measurement. The TA is regulated by delay-locked-loop (DLL) to keep its gain stable under process, voltage and temperature variations. Using full-custom approach, a test chip was designed and implemented in TSMC 0.35-m CMOS process. With an input reference clock of 100MHz, the proposed 13-bit hybrid TDC achieves a resolution of 320ps, a full range of 2.55s and a single-shot precision of 0.73 LSB. The DNL is less than 0.68 LSB and INL is within 1.23 LSB to 1.19 LSB.

Low-jitter DLL applied for two-segment TDC

A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal-oxide-semiconductor process, the measurement results show that DLLs frequency locking range is 60-240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <;1 ns and maximum range of around 1 μs as well as the differential non-linearity <;0.68 LSB and the integration non-linearity within -0.97 to 1.24 LSB are obtained for two-segment TDC.

Compact Active Quenching Circuit for Single Photon Avalanche Diodes Arrays

A compact quenching circuit for Single Photon Avalanche Diode (SPAD) arrays is presented. The proposed circuit preserves the advantages of small area occupation and low power consumption, since it mainly adopts the junction capacitance of the detector to sense the avalanche current. The sensing time is now limited more by the detector rather than the circuit itself. Fabricated in TSMC standard 0.35μm CMOS process, the proposed circuit only occupies an area of 20μm×31μm and can operate properly with the detector biased up to 5V above breakdown. The circuit functionality has been verified by experimental measurements, operating with 64×64 InGaAs/InP single photon avalanche diode arrays for time-of-flight-based applications.

A Novel Time-to-Digital Converter Based on Low-Jitter Phase-Locked Loop

ABSTRACT This paper presents a novel multi-levels time-to-digital converter (TDC) suitable for array architecture for the photon time-of-flight (TOF) measurement. A simple method was applied to solve the initial phase time mismatch caused by random occurrence of the TOF start signal. A low-jitter phase-locked loop (PLL) is adopted to provide excellent clocks to the TDC. The proposed PLL–TDC has a good differential nonlinearity (DNL) (±0.4 LSB) and integral nonlinearity (INL) (±0.5 LSB) due to the low-jitter clock and elimination of initial phase time mismatch. The circuit of the low-jitter PLL was implemented in TSMC 0.35 µm standard complementary metal oxide semiconductor (CMOS) process with 3.3 V supply voltage. The measured result of the low-jitter PLL and the simulated result of the TDC show the proposed 14-bit TDC can realize 1.0 ns time resolution and 16 µs maximum range with 125 MHz centre frequency. Under this given frequency, the time interval error (TIE) jitter is 7.8 ps(rms).

A current detecting circuit for linear-mode InGaAs APD arrays

This paper presents a current detecting circuit for linear-mode InGaAs Avalanche Photo Diode (APD) array, which is the interface between APD and readout circuit. The detecting circuit adopts a Regulated Cascode (RGC) transimpedance preamplifier (TIA) for its high gain and wide bandwidth, and a differential voltage amplifier with high common-mode rejection ratio and strong capability in depressing the noise influence is used to further amplify the sensed signal generated by the preamplifier effectively. A gated control technique is also used to reduce the average power consumption. The circuit is designed and fabricated in TSMC 0.35μm CMOS technology, and the power consumption is 0.73mW with the operating voltage of 3.3V. The core area of the circuit is only 55μm×90μm. The proposed circuit is successfully used in a 8×8 APD array readout circuit, and the experimental result shows that the current sensitivity is 5.2μA.

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixels detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

High-accuracy and compact quenching circuit for InGaAs SPADs

In 3D imaging application, large scale of SPAD arrays, low power consumption, compact and high accuracy quenching circuit is necessary. In this paper we developed a simple and fast pulse sensing circuit with negligible static power dissipation, and the afterpulsing effects are also significantly reduced by fast quenching process. The gated mode is used and it can precisely set the turn-off time of each frame. Ensure SPAD is more reliable. Compare to other active quenching circuits (AQC) for SPADs, the proposed circuit is ultra fast in signal pulse sensing and accurate in time resolution with a low threshold, and it can be easily utilized in SPAD-array detectors for photon-flight-time measurement with sub-nanosecond precision. The quenching circuit implemented by CSMC 0.5-μm CMOS technology is optimal designed by using SPICE simulator, where an accurate SPICE model we established for InGaAs SPAD is embedded. The simulation result shows that the proposed AQC can operate properly in all the static and transient states, and the rising time of the sensed voltage pulse can be caught in 1ns, and its quenching time is less than 5ns. This is much suitable for picosecond precision infrared sensing system.

A low voltage 8.4 ppm/°C voltage reference based on subthreshold MOSFETs

A CMOS voltage reference based on subthreshold operation is proposed. The current mirror mismatch error resulting from the channel length modulation effect is improved by using a self-cascode operational amplifer. The reference generates a constant reference voltage of 639 mV at supply voltage of 1.2V with power consumption of 18uW at room temperature fabricated in CSMC 0.18um CMOS technology. It achieves a temperature coefficient of 8.4ppm/°C for the temperature range from •20 °C to 120 °C