Liyu Yang

Liquid dispensing encapsulation in semiconductor packaging

Liquid encapsulation techniques have been used extensively in advanced semiconductor packaging, including applications of underfilling, cavity‐filling, and glob top encapsulation. Because of the advanced encapsulation materials and the automatic liquid dispensing equipment involved, it is very important to understand the encapsulation material characteristics, equipment characteristics, encapsulation process development techniques in order to achieve the encapsulation quality and reliability. In this paper, the authors will examine the various considerations in liquid encapsulation applications and address the concerns on material characterization, automatic liquid dispensing equipment/process characterization and the encapsulation quality and reliability. The discussions will be helpful for future material and process development of semiconductor packages.

Assessment of acceleration models used for BGA solder joint reliability studies

Abstract Solder joint reliability was one of the top priorities when evaluating the reliability of electronic packages. In general, an acceleration model would be used to predict solder joint fatigue life in the use conditions. However, the accuracy of the model was difficult to validate. As a result, the fatigue life of the solder joints could be over-designed with added cost or time, or under-estimated with a compromised reliability performance. It was an important goal for engineers to use valid and accurate life models to predict the field life of the solder joints and reduce development cost and time. Many empirical models including Norris–Landzberg model and its modifications usually considered the effects of temperature range, the cycle frequency, and the maximum temperature. No matter what the package structures were or the materials were used, engineers had been using the same model parameters for many years. Moreover, little was done to validate the models for modern packages structures and materials. In this article, a variety of package was studied and the failure data was analyzed through a reliability engineering approach. The results showed that the available model parameters were not suitable to predict the solder joint life of test samples exclusively. A new set of model parameters might be required for certain cases. Also, the acceleration factor models would depend on the solder joint materials and microstructures. The solder joint fatigue life performance was too complicated to be assumed as a fixed empirical model. One of the reasons was there were too many factors affecting the strain which the solder joints would endure. In the future study, critical factors such as materials or structures could be integrated into the current model format. Additionally, the ramp rate could be a concern especially when dealing with cases under thermal shock conditions. The methodology to develop an acceleration factor model and the demonstration of their weakness would help achieve reliable solder connections in the future.

Failure rate estimation of known failure mechanisms of electronic packages

Product reliability is one of the key factors for a successful product launch. However, electronic components can still fail in various stages of applications due to certain failure mechanisms. A constant failure rate typically describes a majority of non-solder joint related package failures in the accelerated testing or the field application. Historically, the failure rate for a constant failure phenomenon is estimated by using the Chi-square value or the expected number of failures. This paper will discuss the statistical characteristics of the number of failures observed in tests or applications and their confidence bounds. Several methods used to estimate the confidence bounds will be described, and a new approach will be proposed and validated through case studies. The estimation of the acceleration factor (AF) used in the failure rate modeling is also discussed. The conclusion will help engineers to understand the statistical meaning of the failures observed in stress tests or in the field applications, additionally, obtain a meaningful failure rate based on the expected failure data.

The impact of lead‐free soldering on electronics packages

This paper will review the challenges brought by lead‐free soldering and some preliminary experimental evaluation results will be discussed. The initial results show that the lead‐free soldering process with 260°C reflow peak temperature does not directly cause failures for bismaleimide‐triazine (BT)‐based fine pitch ball grid array (FPBGA) packages. However, the strict lead‐free soldering condition could degrade the integrity of weak interface joints and potentially damage the package in subsequent unbiased highly accelerated stress test (unbiased HAST) evaluation. The impacts of lead‐free soldering with high reflow temperature on concurrent available electronics components could be more severe than previously believed. In the future, new materials and design concepts should be applied to enhance the package reliability under strict lead‐free soldering conditions.

Design‐for‐reliability implementation in microelectronics packaging development

Purpose – In todays electronic package development cycle, activities are managed by multiple participants in the supply chain, which might have different quality and reliability impacts to the end product. As a result, the reliability risk is much higher for companies who do not have insight into and/or control over the products received. The purpose of this paper is to show how design‐for‐reliability (DFR) approaches will come into play to manage the risk.Design/methodology/approach – In this paper, DFR approaches for package development will be discussed from the perspective of the original equipment manufacturers (OEMs). DFR practices through the package development cycle will be described based on key development modules. A case study for flip chip ball gris array package development using an advanced Cu/Low‐k silicon technology will be presented. Key measures to help control the quality and improve the reliability will be presented.Findings – The proposed methodology significantly improves component...

Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon

The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm2) and the die size (approximately 15 mm2 ) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.

Reliability improvement study of a build-up wire bonding EBGA package using eight-layer 0.13 /spl mu/m copper silicon technology

In this paper, the authors discuss the die cracking/thin film delamination failures seen in 8-layer 0.13 mum silicon during the development of an EBGA package with 45 mm times 45 mm body size. The die size was 15.2 mm per side with over 1400 wire bonded pads. The large package body size and die size provided both manufacturing and reliability challenges. It was pointed out that, due to the large die size and complex 8-layer metal silicon process used, the reliability performance heavily relies on the optimization of the wafer sawing process, and stress distributed on the silicon, thin film adhesion, test conditions and assembly variations. Failure analysis demonstrated that cracks initiated from the die edge and then propagated through the interface of M1/silicon interfaces, at certain point, the cracks turn to the surface shown as die cracking. The experimental result showed optimized dual step cut wafer sawing can significantly reduce the risks of die cracking/thin film delamination, the failure rate can be reduced from ~30% to ~5%. It was also observed that units from various lots are performing significantly different during the reliability testing. Finite element study also showed low stress encapsulation materials helps reduce the tensile stress applied on the die edge, and reduce the risk for die cracking. In the future, additional research will be carried out to understand if the metal density in the scribe is playing a significant role, how the cracks initiated and propagated at what steps

Encapsulation process development for flexible-circuit based chip scale packages

The ultimate driving forces for the development of small form-factor chip scale packages (CSPs) are the market demands for small, light and high performance products. The flex-based /spl mu/BGA technology has been a very successful package format, and tremendous efforts have been implemented in the process development for the technology. In this article, three flex-based chip scale packages (based on patented /spl mu/BGA technology) will be discussed. The focus will be on the encapsulation process development. Because of the unique package structures and material sets used in the flex-based CSPs, various encapsulation challenges were raised. The encapsulation solutions are compared and discussed for each type of flex-based /spl mu/BGA technologies, including the dispensing pump technologies, material characterization, process characterization and optimization. Based on the evaluation results, type C /spl mu/BGA technology is recommended for its simple assemble process flow, balanced protection on beam leads and solder ball joints and shorter manufacturing cycle time as well.

Reliability evaluation and modeling of high density electronic packages

Purpose – The purpose of this paper is to describe key failure mechanisms observed during the development of the advanced packaging technology. Extensive accelerated stress tests are conducted to collect failure data and understand failure characteristics and failure trends. The results will be useful for design improvement and failure rate predictions.Design/methodology/approach – High density chip scale packages (CSP) are developed to meet the needs for high performance and small form‐factor products, but with reduced process procedures and product cost. Test‐to‐failure approaches are applied to evaluate the failure rate and reliability models instead of compliance qualification testing approaches.Findings – The study shows Cu‐trace cracking failure can be treated as random failures and analyzed using a constant failure rate approach. The acceleration factor for the Cu‐trace cracking failure mechanism exhibits a large power exponent comparing to the parameters used in reference models. In addition, the ...

Design-for-Reliability applications in concurrent engineering practices for electronic package development from system manufacturers' perspectives

In todays electronic package development cycle, activities are managed by multiple participants in the supply chain which might have different quality and reliability impacts to the end product. As a result, the reliability risk is much higher for companies who do not have insight into and/or control over the products received. Design-for-Reliability (DFR) approaches will come into play to manage the risk. In this article, DFR approaches for package development will be discussed from the perspective of the original equipment manufacturers (OEMs). DFR practices through the package development cycle will be described based on key development modules. A case study for FCBGA package development using an advanced Cu/Low-k silicon technology will be presented. Key measures to help control the quality and improve the reliability will be presented. The DFR methodology will be helpful for fabless design houses, electronics manufacturing service (EMS) partners in the supply chain, and OEMs to manage the reliability of the products.