Lloyd E. Peppard

String stability of relative-motion PID vehicle control systems

An important performance criterion for moving vehicle longitudinal control systems is string stability in the face of perturbations in the motion of individual vehicles. Systems employing a moving-cell reference for each vehicle always exhibit string stability since there is no vehicle interaction within the string. This correspondence investigates the string stability for a class of relative-motion systems where a moving-cell position reference is not available. It is shown that string stability can be achieved only by using both forward and rearward intervehicle separation measurements.

A Fast VLSI Multiplier for GF(2 m )

Multiplication in the finite field GF(2^{m} ) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication in GF(2^{m} ), which is O(m) in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.

Feature-based classification of myoelectric signals using artificial neural networks.

A pattern classification system, designed to separate myoelectric signal records based on contraction tasks, is described. The amplitude of the myoelectric signal during the first 200 ms following the onset of a contraction has a non-random structure that is specific to the task performed. This permits the application of advanced pattern recognition techniques to separate these signals. The pattern classification system described consists of a spectrographic preprocessor, a feature extraction stage and a classifier stage. The preprocessor creates a spectrogram by generating a series of power spectral densities over adjacent time segments of the input signal. The feature extraction stage reduces the dimensionality of the spectrogram by identifying features that correspond to subtle underlying structures in the input signal data. This is realised by a self-organising artificial neural network (ANN) that performs an advanced statistical analysis procedure known as exploratory projection pursuit. The extracted features are then classified by a supervised-learning ANN. An evaluation of the system, in terms of system performance and the complexity of the ANNs, is presented.

Architectures for exponentiation in GF(2/sup m/)

Several VLSI architectures for performing exponentiation in GF(2/sup m/) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2/sup ei/ power, O >

VLSI implementation of public-key encryption algorithms

This paper describes some recently successful results in the CMOS VLSI implementation of public-key data encryption algorithms. Architectural details, circuits, and prototype test results are presented for RSA encryption and multiplication in the finite field GF(2m). These designs emphasize high throughput and modularity. An asynchronous modulo multiplier is described which permits a significant improvement in RSA encryption throughput relative to previously described synchronous implementations.

Implementation of a Viterbi Processor for a Digital Communications System with a Time-Dispersive Channel

This paper describes the theory, design, and testing of a Viterbi processor for a digital communication system with intersymbol interference over fading time-dispersive channels. The requirement is to implement the Viterbi algorithm for a channel memory of 9 baud at a data rate of 2400 bits/s. The processor is partitioned into three subprocessors corresponding to the correlation, state metric evaluation, and state decision-making operations. For prototype evaluation, each subprocessor is being implemented as a separate chip using 4-5 \mu m CMOS technology. The architecture, circuit design, and subsystem characterization of the correlator chip are described in some detail. The chip is required to evaluate 1024 state transition metrics in each baud interval (about 400 ns) using a pipeline architecture. Simulation and initial test results verify the correct operation of the chip with an adequate-speed safety margin. The theory of operation and architecture of the state metric chip are described. With off-chip memory for state metric storage, the state transition metrics from the correlator chip are used to determine the winning (optimal) path in the Viterbi trellis and to calculate the corresponding 16-bit state metric for each baud interval. Implementation of the third chip which is required to make a state decision regarding the bit sequence sent is presently being investigated.

On the Design of SP Networks From an Information Theoretic Point of View

The cryptographic strength of an SP network depends crucially on the strength of its substitution boxes (S-boxes). In this paper we use the concept of information leakage to evaluate the strength of S-boxes and SP networks. We define an equivalence class on n×n S-boxes that is invariant in information leakage. Simulation results for a 16×16 SP network suggest that after a sufficient number of rounds the distribution of the output XOR in the SP network looks random. We further present simulation results to show that the information leakage for an SP network diminishes more rapidly with the number of rounds when the S-boxes are cryptographically strong.

New fault tolerant techniques for residue number systems

Previously proposed error detection algorithms for the residue number system require a complete recombination. A weighted approximation via the Chinese remainder theorem is shown to be sufficient to detect 100% of single errors. This makes real-time single-error diagnosis possible, which involves up to N+2 iterations of detection (N is the number of nonredundant channels). One approach uses a scaled range of L+1+log/sub 2/ (N+1) bits for detection in contrast with full decoding of approximately=L(N+1) bits, where L is the number of bits in the largest modulus. A second method forms a redundant residue number representation of the overflow multiplier A(x), although A(x) does not need to be carried through processing operations. This permits real-time single-error diagnosis and correction with a parallel array of approximately=(N+2)/sup 2/ tables. >

A design of a fast pipelined modular multiplier based on a diminished-radix algorithm

We present a new serial-parallel concurrent modular-multiplication algorithm and architecture suitable for standard RSA encryption. In the new scheme, multiplication is performed modulo a multiple of the RSA modulus n, which has a diminished-radix form 2k-v, where k and v are positive integers and v < n. This design is the first concurrent modular multiplier to use a diminished-radix algorithm and to pipeline concurrent modular-reduction to optimize the clock rate. For a modular multiplier of order ranging from 1 to 10 (number of multiplier bits per clock cycle), a faster clock rate and throughput is possible than with other known designs including those of Brickell, Morita, Sedlak and Golze, and Miyaguchi. Throughput estimates for 512-bit RSA decryption range from 100 kbit/s in a serial mode to 650 kbit/s with a modular multiplier of order 10, at a clock rate of 20 MHz on 1.5 μm CMOS.

Moving-cell vehicle control over nonlevel terrain

The application of a proportional-integral-differential (PID) control scheme to the problem of regulating the longitudinal motion of vehicles traversing nonlevel terrain is presented. A third-order representation of the vehicle dynamics is used, and a moving-cell (fixed reference) controller is designed using pole placement techniques. Analog computer simulation results are presented.