Lorenzo Guerrieri

Performance of the turbo coded HomePlug AV system over power-line channels

The next generation technology of HomePlug, called HomePlug AV, aims at providing very high-quality connectivity for the in-home distribution of data and multi-stream entertainment using existing power-line wiring. To obtain very robust performance a powerful turbo convolutional code is adopted. In this paper, by means of simulations, the performance of the turbo coded HomePlug AV system is examined under a realistic power-line channel model. In particular, the effects of the interleavers length and of the number of iterations in an improved Max-Log-MAP turbo decoder are investigated. Results show that few iterations of the turbo decoding process give a massive gain in performance under the considered environment.

Multipath Modeling of Automotive Power Line Communication Channels

In this paper, an in-vehicle power line channel mathematical multipath representation is proposed. The selected approach aims at describing the transmission of a signal on a possibly complex power network by means of a finite number of delayed echoes. Model parameters are computed via a well-defined step-by-step procedure from frequency-domain channel characteristics. The feasibility and strength of the method are demonstrated by means of a measurement campaign. Two-port scattering measurements have been carried out on a commercial automobile and the effect of the measurement setup has been considered in the analysis.

Statistical assessment of automotive PLC multipath channel models

This paper addresses the modeling of in-vehicle power line communication channels via multipath parametric representations. The study is based on a set of frequency-domain measurements carried out on a commercial automobile. The proposed procedure for the computation of model parameters from real measured data is briefly summarized and a systematic assessment aimed at collecting some useful statistical information on both the estimated models and the channel features is thoroughly discussed. Specific emphasis is given to the definition of the range of the key parameters that allow characterizing real automotive PLC channels.

Experimental field trials of a utility AMR power line communication system analyzing channel effects and error correction methods

This paper analyses the effects of noise in a real automated meter reading (AMR) environment where power line communication (PLC) is used for meter reading. The aim is to give an analysis of periodic noise properties through its effect on a B-FSK based PLC system and to compare different error correction techniques under different constraints of attenuation and noise produced by the real loads installed in the network. Tests have been carried out using two different channel frequencies in the CENELEC A band taking into account frequency dependence of the line.

HomePlug AV system and DLC bit-loading algorithm over OPERA power-line channels with impulsive noise

In this paper, the higher data rate technology of HomePlug, called HomePlug AV, is tested over the power-line channel models proposed by the OPERA project coupled with the Middleton Class A impulsive noise model. In particular, the performance of the recently proposed DLC bit-loading algorithm is analyzed in terms of throughput when different scenarios are considered. Simulations show that the effects of the impulsive noise can be reduced by inserting a clipping module before the OFDM demodulator, thus guaranteeing very promising throughputs even in the worst scenarios.

Stopping Rules for Duo-Binary Turbo Codes and Application to HomePlug AV

This paper focuses on the design of stopping rule criteria for duo-binary turbo codes. In particular, single-binary stopping rules are generalized and iteration/semi-iteration based criteria are developed. The proposed solutions are tested using the framework of HomePlug AV, which is the last generation technology for the in-home distribution of audio and video data over existing power-line wiring.

Improved spread frequency shift keying receiver

This paper presents a novel method of estimating log-likelihood ratios and a receiver for spread frequency shift keying modulation. This new solution is compared in terms of memory occupation, required operations and BER performance with the ideal theoretical solution and two suboptimal solutions previously presented in the literature. Furthermore, through numerical simulations, the improvements of the proposed solution are shown in terms of BER performance.

LLR- based Bit- loading Algorithm and its Applications to HomePlug AV over OPERA Power- line Channels with Impulsive Noise

In this paper the higher data rate technology of HomePlug, called HomePlug AV, is tested over the power-line channel models proposed by the OPERA project coupled with the Middleton Class A impulsive noise model. In particular the DLC bit-loading algorithm is developed and the performance is analyzed in terms of throughput when different scenarios are considered. To better exploit the error correction capabilities of the turbo code, this bitloading algorithm attempts to maximize the throughput while guaranteeing a target BER over a set of sub-carriers using a new metric based on the LLRs. Simulations show that the effect of the impulsive noise can be reduced by inserting a clipping module before the OFDM demodulator, thus guaranteeing very promising throughputs even in the worst scenarios.

Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator

This paper addresses the design of a channel emulator for the data communication along in-vehicle power distribution networks. Power-line communication technology is a promising solution that uses the same physical bundle of wires supplying energy to the large number of components spread within a car, with benefits in terms of budget and weight saving. The communication channel is described by means of a multipath representation while the different noise contributions, supported by a dedicated measurement campaign, include impulsive and very low-frequency disturbances. The channel emulator is designed on a Virtex-6 FPGA with a target working frequency of 200 MHz. The proposed emulator has very high programmability and is proven to provide superior performance in terms of bandwidth compared to the known state-of-the-art hardware nonautomotive alternatives.

Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation

HomePlug AV is the most successful standard for in home power line communications. To combat non-ideality of the power line channel it includes a double binary turbo forward error correcting scheme. Unfortunately, it is known that the memory required by double binary turbo decoders for iteration-exchanged information is roughly three times the memory required for binary turbo codes. Moreover, high throughput implementations based on border state metric inheritance, require additional memories to store border state metrics from an iteration to the next one. This work faces these two aspects by analyzing compression techniques to reduce the amount of memory required to store both iteration-exchanged information and border future metrics. Experimental simulations show that non-uniform quantization and least significant bits dropping allow for a significant memory reduction (up to 30%) with a bit error rate performance loss of about 0.1 dB and a negligible logic gates overhead.