Louis Arpin

System Architecture of the LabPET Small Animal PET Scanner

To address modern molecular imaging requirements, a digital positron emission tomography (PET) scanner for small animals has been developed at Universite de Sherbrooke. Based on individual readout of avalanche photodiodes (APD) coupled to LYSO/LGSO phoswich detectors, the scanner supports up to 4608 channels in a 16.2 cm diameter, 11.25 cm axial field of view with an isotropic ~ 1.2 mm FWHM intrinsic spatial resolution at the center of the field of view. Custom data acquisition boards preprocess and sample APD signals at 45 MHz and compute in real time crystal identification, energy and timing information of detected events at an average sustained rate of up to 1250 raw counts per second per mm2 (10 000 cps/channel). Real time digital signal analysis also filters out events outside the pre-selected energy window with crystal granularity to eliminate Compton events and electronic noise. Retained events are then merged into a single stream through a real-time sorting tree, at which end prompt and delayed coincidences are extracted. A single Firewire link handles both control and data transfers with a host computer. The LabPET features four data recording modes, giving the user the choice to retain data for research or to minimize file size for high coincidence count rate and imaging purposes. The electronic system also supports time synchronized data insertion for flags such as vital signs used in gated image reconstruction. Aside from data acquisition, hardware can generate live energy and discrimination spectra suitable for fast, automatic channel calibration.

System Integration of the LabPET Small Animal PET Scanner

To address modern molecular imaging requirements, a digital positron emission tomography scanner for small animals has been developed at Universite de Sherbrooke. Based on individual readout of avalanche photodiodes (APD) coupled to a LYSO/LGSO phoswich array, the scanner supports up to 3072 channels in a 16.2 cm diameter, 7.5 cm axial field of view with an isotropic 1.2 mm FWHM intrinsic spatial resolution at the center of the FOV. Custom data acquisition boards sample APD signals at 45 MHz and compute in real time crystal identification, energy and timing information of detected events at rates of up to 1250 raw counts per second per mm2 (10k cps/channel). Real time digital signal analysis also filters out events outside the photopeak with crystal granularity to eliminate Compton events and electronic noise. Retained events are then merged into a single stream through a real-time sorting tree, at which end the prompt and delayed coincidences are extracted. A single Firewire link handles both control and data transfers with a computer. The LabPETtrade features four data recording modes, giving the user the choice to retain data for research or to minimize file size for high coincidence count rate and imaging purposes. The electronic system also supports time synchronized data insertion for flags such as vital signs used in gated image reconstruction. Aside from data acquisition, hardware can generate live energy and discrimination histograms suitable for fast, automatic channel calibration.

A Sub-Nanosecond Time Interval Detection System Using FPGA Embedded I/O Resources

The Time to Digital Converter (TDC) concept is quite useful to obtain crucial timing information for nuclear radiation detection such as PET imaging applications. The high resolution nature of TDCs makes them sensitive to process and temperature variations. Thus, a calibration procedure must often be performed to improve measurements. Moreover, field programmable gate array (FPGA)-based TDC exacerbates this problem because the transistor topology is fixed on the fabric for low cost purposes. A Sub-Nanosecond Time Interval Detection System, able to overcome process and temperature (PT) variations, was designed and implemented in an FPGA. Unlike other FPGA-based TDCs, this new solution uses embedded PT invariant digital delay lines and deserializers included in I/O ports, along with a stable clock oscillator resulting in low logic usage. The proposed design consists of oversampling digital signals to enable the creation of absolute timestamps down to 75 ps resolution (31.85 psRMS). As a proof of concept, this paper reports timing resolution down to 321.5 ps.

Embedded real time digital signal processing unit for a 64-channel PET detector module

Recent developments in avalanche photodiode (APD) technology have led to the design and fabrication of a new radiation detector module based on an 8 × 8 array of LYSO crystals individually coupled to the pixels of two 4 × 8 monolithic APD arrays. This evolution entails the complete redesign of the data acquisition system to satisfy the 7-fold increase in pixel density relative to a previous implementation of individually read out sensors. As a result, the required digital signal processing cannot be implemented exclusively in FPGAs due to cost, area occupied and power consumption considerations. To comply with this new reality, a 64-channel mixed-signal ASIC, built from TSMC CMOS 0.18 µm technology, has been designed. It uses a Time-over-Threshold (ToT) scheme to extract both energy and timing along with the pixel number. A complex architecture of finite state-machines, driven by a 100 MHz clock, ensures the ASIC real time ToT calculation operations and its proper calibration by an external device. The ASIC can output as much as 2 Mevents/s on its LVDS data transfer dedicated link and consumes around 600 mW. The ASIC was developed following a mixed-signal flow allowing the designers to minimize and to verify the impact of undesirable parasitic effects on both analog and digital ends of the ASIC before sending the layout to the foundry.

A fully integrated pulse charge generator embedded in a 64-channel readout ASIC dedicated to a PET/CT detector module

The LabPETTM II is a new Positron Emission Tomography/Computed Tomography (PET/CT) scanner dedicated to small animals imaging under development at the Université de Sherbrooke. Its design requires nearly 37 000 detectors spread over a ring of 15 cm in diameter and 12 cm of axial length. This new scanner will break the submillimetric spatial resolution barrier in PET mode thanks to a new double 4 × 8 array of 1.1 × 1.1 mm2 avalanche photodiode (APD) coupled to an 8 × 8 LYSO crystal matrix. In order to readout individually each pixel of this detector block, a 64-channel Application Specified Integrated Circuit (ASIC) was developed based on Time-over-Threshold (ToT) technique. The ToT computations allow the extraction of both the energy and time of occurrence of PET signals. There are also adjustable gains located in each individual analog front-end chain that enables the detection of low energy X-ray photons (~ 42 keV) required for CT imaging mode. As a result of the complexity of this fully mixed-signal chip, calibrating the scanner and testing every single channel can be a cumbersome job on PCB using an external charge injector equipment. To facilitate those operations, a fully integrated pulse charge generator (PCG) was designed for the LabPET™ II ASIC. The PCG injects a 3-bit adjustable amount of charge in each channel in order to verify their impulse response and to calculate intrinsic energy and time resolution for both PET and CT modes. It can also be used to evaluate the analog front-end electronics noise, by knowing the electronic gain of each channel individually. The PCG can inject a charge that ranges from 35 fC to 56 fC by steps of 2.6 fC in PET mode and from 2.3 fC to 5.1 fC in steps of 0.3 fC at a rate of 1 kHz.

Performance characterization of a dual-threshold time-over-threshold APD-based detector front-end module for PET imaging

The LabPET II front-end module is an avalanche photodiode (APD) based pixelated detector designed to achieve submillimetric spatial resolution in pre-clinical Positron Emission Tomography (PET). This technology is also based on Time-over-Threshold (ToT) signal processing and designed to be used as a generic platform for ultra-high resolution PET imaging of small and medium-size animals. The basic building block uses a 4×8 array of 1.12×1.12×12 mm3 Lu1.9Y0.1SiO5:Ce (LYSO) scintillator pixels with one-to-one coupling to a 4×8 pixelated APD array mounted on a ceramic carrier. Four of these detectors are mounted on a PCB with two 64-channel ASICs interfacing to two detector modules each. Signals from each APD pixel can be individually processed by dedicated dual-threshold ToT channels providing timing and energy data. Energy calibration was performed using gamma ray sources in the range 300-1275 keV to correct the non-linearity of the ToT signal and obtain energy spectra. Energy and timing performance of the complete front-end module was evaluated. Results confirm the functionality of the dual threshold ToT circuit implemented in the 64-channel ASIC, as well as the physical performance of the most recent LabPET II version of APD-based detectors for applications in high-resolution PET imaging.

A Delay Locked Loop for fine time base generation in a positron emission tomography scanner

In this paper, an analog Delay Locked Loop with fixed latency of one clock cycle is proposed. It was implemented with differential delay cells in order to reduce noise, and based on a precise dynamic phase comparator. With a 1.8 V supply and a 100 MHz input clock, the DLL consumes 3.4 mW and the measured jitter is 3.9 ps rms. It was implemented on a 0.18 μm TSMC CMOS technology and occupies an active area of 0.0022 mm2.

Firmware architecture of the data acquisition system for the LabPET II mouse scanner

A new, highly pixelated, PET scanner dedicated to mouse imaging is being developed based on the LabPET II detector module. Each module includes four monolithic array of 4×8 avalanche photodiodes (APD) individually coupled to four 4×8 array of 1.12×1.12 mm2 scintillator pixels aimed at achieving submillimetric spatial resolution. A PCB routes the signals from four detector arrays to two 64-channel, mixed-signal, Application Specific Integrated Circuit (ASIC), forming a 128-channel readout unit. A new DAQ system was designed to interface this novel detector module. Its firmware architecture consists of 2 types of custom FPGA-based electronic boards processing data from the detector module. An embedded signal processing unit is in charge of data readout, corrections and sorting. It also features live energy histogramming and count rates computation. An FPGA-based coincidence, data communication and gating unit collects data from all embedded signal processing units and deals with coincidence detection together with random estimation and sends processed data to a host computer. In parallel to the detected events stream, a command and control flow was added for ASIC automatic calibration, electronic boards parameters setting and readout from the host computer. This firmware allows a real-time PET data processing without degrading the detector module performance.

Initial results for automatic calibration of the LabPET II front-end detector module

An automatic calibration process for the LabPET II detector front-end module has been developed. By aiming at sub-millimetric spatial resolution, an unprecedented channel density is reached. The new detector front-end module is based on an application-specific integrated circuit (ASIC) implementing a Time-over-Threshold (ToT) scheme to extract both energy and time information. Consequently manual channel calibration becomes a tedious task and an automatic calibration strategy adapted to the ToT scheme is required to cope with the huge number and complexity of detector channels. The calibration process involves four main tasks: Clock Phase Adjustment, Photopeak Alignment, Timing Optimization and Energy Correction. To grant an easy and frequent adjustment, the calibration routine must be automatic and real-time. It was implemented in VHDL and C on a Microblaze microprocessor core embedded in a field programmable gate array (FPGA). Misalignment between channels were reduced after calibration from 17% FWHM to 6% FWHM.

A Sub-Nanosecond Edge Detection System using embedded FPGA fabrics

The Time to Digital Converter (TDC) concept is quite useful to obtain crucial timing information for nuclear radiation detection such as PET imaging applications. The high resolution nature of TDC makes them sensitive to processing and to temperature variations. Thus, a calibration procedure must often be performed to improve measurements. Moreover, field programmable gate array (FPGA)-based TDC exacerbates this problem because the transistor topology is fixed in the fabric for low cost purpose. A Sub-Nanosecond Edge Detection System able to overcome process, power supply voltage and temperature (PVT) variations was designed and implemented in an FPGA. Unlike other FPGA-based TDCs, this new solution uses embedded PVT invariant digital delay lines and deserializers included in I/O ports along with a stable clock oscillator resulting in low logic usage. The proposed approach consists in oversampling digital signals to enable absolute timestamps down to 75 ps resolution (31.85 ps rms). As a proof of concept, this paper reports timing resolution down to 321.5 ps.