Luan Suzhen

Investigation of frequency dispersion effect in HfO 2 /SiO 2 Gate Stack

The frequency dispersion effect of MOS capacitor with HfO2/SiO2 gate stack is investigated. An equivalent four-element circuit model is presented. Based on this model, frequency dispersion at high frequencies can be eliminated. Experimental results demonstrate the presented model can accurately measure C-V characteristics of MOS capacitor with HfO2/SiO2 gate stack.

Quantum compact model for thin-body double-gate Schottky barrier MOSFETs

Nanoscale Schottky barrier metal oxide semiconductor field-effect transistors (MOSFETs) are explored by using quantum mechanism effects for thin-body devices. The results suggest that for small nonnegative Schottky barrier heights, even for zero barrier height, the tunnelling current also plays a role in the total on-state current. Owing to the thin body of device, quantum confinement raises the electron energy levels in the silicon, and the tradeoff takes place between the quantum confinement energy and Schottky barrier lowering (SBL). It is concluded that the inclusion of the quantum mechanism effect in this model, which considers an infinite rectangular well with a first-order perturbation in the channel, can lead to the good agreement with numerical result for thin silicon film. The error increases with silicon thickness increasing.

The influence of source and drain junction depth on the sub-50nm MOSFET devices

This brief investigates the influence of source and drain junction depth on the short-channel effect (SCE) in highly scaled MOSFETs. It is shown using two-dimensional finite-element device simulation that the influence of source and drain junction depth on SCE can be represented by an additional of a pre-exponential term to the established scale-length model. For source and drain junction depths that are deeper than the MOSFETs gate depletion-layer width, SCE is shown with this pre-exponential term to be insensitive to junction depth. Conversely, for source and drain junction depths that are shallower than the MOSFETs gate depletion-layer width, SCE is shown to improve with decreasing junction depth. Finally, the influence on off-current of source and drain junction depths is given