Luca G. Fasoli

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-/spl mu/m CMOS substrate. One-time programming is performed by applying a high voltage across the cell terminals, which ruptures the antifuse and permanently encodes a logic 0. Unruptured antifuses encode a logic 1. Cells are arranged in 8-Mb tiles, 1 K rows by 1 K columns by 8 bits high. The die contains 72 such tiles: 64 tiles for data and eight tiles for error-correcting code bits. Wordline and bitline decoders, bias circuits, and sense amplifiers are built in the CMOS substrate directly beneath the memory tiles, improving die efficiency. The device supports a generic standard NAND flash interface and operates from a single 3.3-V supply.

512 Mb PROM with 8 layers of antifuse/diode cells

A 3.3 V, 512 Mb PROM uses a transistorless memory cell containing an antifuse and diode. A bit area of 1.4F/sup 2/ including all overhead is achieved by stacking cells 8 high above the 0.25 /spl mu/m CMOS substrate. Read bandwidth is 1 MB/s and write bandwidth is 0.5 MB/s. A 72 b Hamming code provides fault tolerance.

A 130.7mm 2 2-layer 32Gb ReRAM memory device in 24nm technology

ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have been used for several megabit test-chips and memory macros [1-3]. This paper presents a MeOx-based 32Gb ReRAM test chip developed in 24nm technology.

A 130.7-

A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die efficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to compensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption being dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.