Luca Larcher

Metal oxide resistive memory switching mechanism based on conductive filament properties

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament (CF) features controlling TiN/HfO2/TiN resistive memory (RRAM) operations. The leakage current through the dielectric is found to be supported by the oxygen vacancies, which tend to segregate at hafnia grain boundaries. We simulate the evolution of a current path during the forming operation employing the multiphonon trap-assisted tunneling (TAT) electron transport model. The forming process is analyzed within the concept of dielectric breakdown, which exhibits much shorter characteristic times than the electroforming process conventionally employed to describe the formation of the conductive filament. The resulting conductive filament is calculated to produce a non-uniform temperature profile along its length during the reset operation, promoting preferential oxidation of the filament tip. A thin dielectric barrier resulting from the CF tip oxidation is found to control filament resistance in the high resistive state. Field-driven dielectric breakdown of this barrier during the set operation restores the filament to its initial low resistive state. These findings point to the critical importance of controlling the filament cross section during forming to achieve low power RRAM cell switching.

Modeling and Optimization of a Solar Energy Harvester System for Self-Powered Wireless Sensor Networks

In this paper, we propose a methodology for optimizing a solar harvester with maximum power point tracking for self-powered wireless sensor network (WSN) nodes. We focus on maximizing the harvesters efficiency in transferring energy from the solar panel to the energy storing device. A photovoltaic panel analytical model, based on a simplified parameter extraction procedure, is adopted. This model predicts the instantaneous power collected by the panel helping the harvester design and optimization procedure. Moreover, a detailed modeling of the harvester is proposed to understand basic harvester behavior and optimize the circuit. Experimental results based on the presented design guidelines demonstrate the effectiveness of the adopted methodology. This design procedure helps in boosting efficiency, allowing to reach a maximum efficiency of 85% with discrete components. The application field of this circuit is not limited to self-powered WSN nodes; it can easily be extended in embedded portable applications to extend the battery life.

A Physical Model of the Temperature Dependence of the Current Through

In this paper, we investigate the characteristics of the defects responsible for the leakage current in the SiO2 and SiO2/HfO2 gate dielectric stacks in a wide temperature range (6 K-400 K). We simulated the temperature dependence of the I -V characteristics both at positive and negative gate voltages by applying the multiphonon trap-assisted tunneling model describing the charge transport through the dielectric. In the depletion/weak inversion regime, the current is limited by the supply of carriers available for tunneling. In strong inversion, the temperature dependence is governed by the charge transport mechanisms through the stacks; in particular, in SiO2/HfO2 dielectric stacks, the coupling of the injected carriers with the dielectric phonons at the trap sites is the dominant mechanism. Matching the simulation results to the measurement data allows extracting important trap parameters, e.g., the trap relaxation and ionization energies, which identify the atomic structure of the electrically active defects in the gate dielectric.

\hbox{SiO}_{2}\hbox{/}\hbox{HfO}_{2}

Power efficiency in switched common source class-E amplifiers is usually obtained at the expense of device stress. Device stacking is a viable way to reduce voltage drops across a single device, improving long-term reliability. In this paper, we focus on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design. In particular, a new dissipative mechanism, peculiar of the cascode implementation, is identified and a circuit solution to minimize its effect is proposed. Prototypes, realized in a 0.13-/spl mu/m CMOS technology demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth was also realized with greater than 60% PAE over the frequency range of 1.4-2 GHz.

Stacks

A new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multiphonon trap-assisted tunneling as conduction mechanism, calculates the total leakage current summing the contributions of the percolation paths formed by one or more aligned traps. Spatial positions and energetic levels of traps have been randomly generated within the oxide by a random number generator which has been integrated into the model. Using this model, statistical simulations of leakage currents measured from both MOS and Flash EEPROM memory tunnel oxides have been carried out. In this way, experimental leakage current distributions can be directly reproduced, thus opening a wide range of useful applications in MOS and Flash EEPROM memory reliability prediction.

Analysis of reliability and power efficiency in cascode class-E PAs

The aim of this paper is to achieve a correct description of the programming charge distribution in NROM memory devices. This is essential to prove device functionality and to extrapolate scaling limits of devices. For this purpose we employ an inverse modeling based methodology using measurements easily performed, such as subthreshold characteristics and threshold voltage measurements. We show a simple model of programming charge distribution that can be easily implemented in two-dimensional (2-D) TCAD simulations. Results show good agreement between measured and simulated currents under different bias conditions and for different programming levels.

Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament features controlling TiN/HfO2/TiN resistive memory operations. The forming process is found to define the filament geometry, which in turn determines the temperature profile and, consequently, the switching characteristics. The findings point to the critical importance of controlling filament dimensions during the forming process (polarity, max current/voltage, etc.).

Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells

We have addressed the problem of threshold voltage (V/sub TH/) variation in flash memory cells after heavy-ion irradiation by using specially designed array structures and test instruments. After irradiation, low V/sub TH/ tails appear in V/sub TH/ distributions, growing with ion linear energy transfer (LET) and fluence. In particular, high LET ions, such as iodine used in this paper, can produce a bit flip. Since the existing models cannot account for large charge losses from the floating gate, we propose a new mechanism, based on the excess of positive charge produced by a single ion, temporarily lowering the tunnel oxide barrier (positive charge assisted leakage current) and enhancing the tunneling current. This mechanism fully explains the experimental data we present.

Metal oxide RRAM switching mechanism based on conductive filament microscopic properties

An analytical model of Radiation Induced Leakage Current (RILC) has been developed for ultra-thin gate oxides submitted to high dose ionizing radiation. The model is based on the solution of the Schrodinger equation for a simplified oxide band structure, where RILC occurs through electron trap-assisted tunneling. The values of the model parameters have been calibrated by comparing the transmission probabilities obtained in this model with those obtained through the WKB method in the actual oxide band structure. No free fitting parameter has been introduced, and all physical constant values have been selected within the values found in literature. Different trap distributions have been considered as candidates, but the comparison between simulated and experimental curves have indicated that a double gaussian distribution in space and in energy grants the best fit of the experimental results for different ionizing particles, oxide fields during irradiation, radiation doses, and oxide thickness. Excellent matching has been found for both positive and negative RILC by using a single trap distribution. The trap density linearly increases with the radiation dose and decreases with the oxide field during irradiation. The trap distribution is spatially symmetrical in the oxide, centered in the middle of the oxide thickness, and is not modified as the cumulative dose increases.

Radiation effects on floating-gate memory cells

We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO2 interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.