Lucas P. B. Lima

Metal gate work function tuning by Al incorporation in TiN

Titanium nitride (TiN) films have been used as gate electrode on metal-oxide-semiconductor (MOS) devices. TiN effective work function (EWF) values have been often reported as suitable for pMOS. For nMOS devices, a gate electrode with sufficient low EWF value with a similar robustness as TiN is a challenge. Thus, in this work, aluminum (Al) is incorporated into the TiN layer to reduce the EWF values, which allows the use of this electrode in nMOS devices. Titanium aluminum (TiAl), Al, and aluminum nitride (AlN) layers were introduced between the high-k (HfO2) dielectric and TiN electrode as Al diffusion sources. Pt/TiN (with Al diffusion) and Pt/TiN/TiAl/TiN structures were obtained and TiN EWF values were reduced of 0.37 eV and 1.09 eV, respectively. The study of TiN/AlN/HfO2/SiO2/Si/Al structures demonstrated that AlN layer can be used as an alternative film for TiN EWF tuning. A decrease of 0.26 eV and 0.45 eV on TiN EWF values were extracted from AlN/TiN stack and AlN/TiN laminate stack, respectively. AlN/TiN laminate structures have been shown to be more effective to reduce the TiN work function than just increasing the AlN thickness.

Dielectrophoretic manipulation of individual nickel nanowires for electrical transport measurements

Nanowires (NW) have received much attention due to their high aspect ratio, shape anisotropy, relatively large surface area and particular electron transport properties. In addition, since NW present low current levels and high sensitivity, they can be used as sensor devices for several applications. One of the major challenges when dealing with transport measurements in NW is to trap them between electrodes, which allow electrical characterization and therefore fabrication of nanowire-based devices. Electrically neutral NW can be deposited by dielectrophoresis (DEP) method, which requires the application of an alternating electric field between electrodes. In this work, properly dispersed Ni nanowires (NiNW) (length = 4 ± 1 μm, diameter = 35 ± 5 nm) were deposited on top of Pt electrodes using the DEP method. The effects of electrodes geometry and electric field frequency on DEP efficiency were evaluated. For optimized DEP parameters, the process efficiency is up to 85%. The deposited NiNW exhibit a Schottky-like current versus voltage behavior due to the high contact resistance between NiNW and electrode. Its reduction down to two orders of magnitude, reaching value less than the NiNW resistance (∼6 kΩ), was achieved by depositing a 10 nm-thick Pt layer over the NW extremities. Therefore, this method presents a selection of adequate electrical DEP parameters and electrode geometry, making it a suitable process of NW deposition and electrical characterization. This can be used for investigation of electrical transport properties of individual NW and fabrication of NW-based devices, like sensors and field effect transistors.Nanowires (NW) have received much attention due to their high aspect ratio, shape anisotropy, relatively large surface area and particular electron transport properties. In addition, since NW present low current levels and high sensitivity, they can be used as sensor devices for several applications. One of the major challenges when dealing with transport measurements in NW is to trap them between electrodes, which allow electrical characterization and therefore fabrication of nanowire-based devices. Electrically neutral NW can be deposited by dielectrophoresis (DEP) method, which requires the application of an alternating electric field between electrodes. In this work, properly dispersed Ni nanowires (NiNW) (length = 4 ± 1 μm, diameter = 35 ± 5 nm) were deposited on top of Pt electrodes using the DEP method. The effects of electrodes geometry and electric field frequency on DEP efficiency were evaluated. For optimized DEP parameters, the process efficiency is up to 85%. The deposited NiNW exhibit a Scho...

Influence of Al/TiN/SiO2 structure on MOS capacitor, Schottky diode, and fin field effect transistors devices

Titanium nitride (TiN) films were tested for their suitability as upper electrodes in metal–oxide–semiconductor (MOS) capacitors and Schottky diodes and as metal gate electrodes in fin field effect transistor devices. TiOxNy formation on TiN surfaces was confirmed by x-ray photoelectron spectroscopy and appears to be associated with exposure of the metal electrodes to ambient air. In order to avoid the formation of TiOxNy and TiO2, a layer of aluminum (Al) was deposited in situ after the TiN deposition. TiN work function was calculated for the devices to study how dipole variation at the interface TiN/SiO2 influences TiN work function. TiOxNy and TiO2 formation at the film surface was found to affect the dipole variations at the TiN/SiO2 interface increasing the dipole influence on MOS structure. Furthermore, the estimated values TiN work function are suitable for complementary metal–oxide–semiconductor (CMOS) technology. Finally, this work had shown that Al/TiN structure can be used in CMOS technology, e...

Fabrication of p-type silicon nanowires for 3D FETs using focused ion beam

A Ga+ focused ion beam (GaFIB) from a FIB/scanning electron microscopy (SEM) dual beam system was used for Si milling and p-type local doping of p+-type silicon nanowires (p+-SiNWs). The resulting p+-SiNWs were then used to create pMOS junctionless nanowire transistor (JNT) prototypes for silicon-on-insulator wafer substrates. The electron beam from the FIB/SEM dual beam system was used to deposit SiO2 gate dielectric and Pt source/drain electrodes for JNT transistors. Width, length, and height dimensions of p+-SiNWs were approximately 35 nm, 6 μm, and 15 nm, respectively, and the JNT gate length was 1 μm. Finally, photolithography, Al sputtering deposition, and lift-off processing were conducted to define the Al gate electrode and contacts on Pt source/drain electrodes. Energy dispersive x-ray spectroscopy measurements were taken to confirm the surface composition of p+-SiNWs and Ga doping. Drain–source current (IDS) versus drain–source voltage (VDS) measurements of JNT transistors indicated that the dev...

Oxygen incorporation and dipole variation in tantalum nitride film used as metal-gate electrode

Tantalum nitride (TaN) films were used as gate electrodes in MOS capacitors fabricated with 8-nm-thick SiO2 as gate dielectric, and also used in Schottky diodes on n-type Si (100) substrates. TaN films with 20- and 100-nm-thick layers presented electrical resistivity of 439 and 472 μΩ cm, respectively. XPS measurements on these TaN film surfaces show oxygen incorporation, which can be related to air exposure. MOS capacitors with TaN/SiO2/Si/Al and Al/TaN/SiO2/Si/Al structures, and Schottky diodes with TaN/Si/Al and Al/TaN/Si/Al structures, were fabricated on the same substrates. These devices were electrically characterized by capacitance–voltage (C–V) and current–voltage (I–V) measurements after sintering in a conventional furnace in a forming gas environment at 450 °C, for different times between 0 and 30 min. From C–V measurements of the MOS capacitors, the extracted TaN work function, effective charge densities, and flatband voltage values were found to be between 4.23 and 4.42 eV, −1011 and −1012 cm−...

Ga+ focused ion beam lithography as a viable alternative for multiple fin field effect transistor prototyping

A novel method for fast and flexible fin field effect transistor (FinFET) prototyping using a Ga+ focused ion beam is presented. The fin width and height control is explored, aiming for the successful fabrication of prototypes. This method results in fins with negligible Ga incorporation, when compared to traditional focused ion beam milling techniques. Our method for multiple fin FinFET prototyping enables advanced device fabrication and great flexibility regarding both the number of fins and fin width. Working FinFET prototypes have been fabricated using the proposed fin definition method, and the electrical characterization is discussed.

Formation and characterization of tin layers for metal gate electrodes of CMOS capacitors

In this study, ultrathin films (thickness of less than 20 nm) of titanium nitride (TiN) to be used as gate electrodes for CMOS (Complementary Metal Oxide Semiconductor) technology were obtained. These ultrathin films were obtained by electron beam evaporation of ultrathin layers (1 or 2 nm thick) of titanium (Ti) followed by ECR (Electron Cyclotron Resonance) plasma nitridation of nitrogen (N2). After deposition and nitridation of the titanium, in order to prevent oxidation of the films, in the same nitriding ECR reactor, a-Si:H (hydrogenated amorphous silicon) films were deposited by CVD (Chemical Vapor Deposition) using SiH4/Ar plasma. These films of a-Si:H were implanted with phosphorus (P+) and annealed by rapid thermal annealing to turn them n+ dopped and polycrystalline. Thus, MOS metal gate electrodes were formed with n+ Poly-Si/TiN structures.