Luciano Boglione

A novel extraction procedure to determine the noise parameters of on-wafer devices

A new procedure for the extraction of noise parameters of on-wafer devices is presented and validated experimentally for the first time. The procedure is based on the noise figure measurement of similar devices of different size and biased at constant drain current density Jds and constant drain voltage Vds. Key to its implementation is a scalable noise model. The model in use is the Pospieszalski noise model, based on the equivalent noise temperatures Tgs and Tds of the gate-source and the drain-source resistance, respectively. The new procedure also outlines a path towards the experimental validation of all the noise temperatures associated with the devices lossy elements.

A noise parameters extraction procedure suitable for on-wafer device characterization

This paper describes a new procedure to extract the noise parameters of on-wafer devices. The procedure is based on multiple noise figure measurements of similar devices of different size and biased at constant drain current density Jds and constant VDS. The theory in support of this novel approach is presented and validated against measurements and simulations. Key to its implementation is a scalable noise model. The model in use is the Pospieszalski noise model, based on the equivalent noise temperatures Tgs and Tds of the gate-source and the drain-source resistance, respectively. The new procedure also outlines a path towards the experimental validation of all the noise temperatures associated with the devices lossy elements.

Power and linearity performance of a cascode InGaP/GaAs HBT distributed amplifier for instrument applications

This paper describes the performance of a cascode InGaP/GaAs HBT distributed amplifier for instrument applications. In particular, the linearity of the distributed amplifier is considered. The compression point, the second and third harmonics, and the third order intercept point have been measured over different bias conditions. At nominal bias, the amplifier delivers a P1dB of 20 dBm and a TOI of 30 dBm up to 20 GHz. This amplifier can achieve simultaneously some of the best results published in the literature.

A Fully Integrated Broadband Sub-mmWave Chip-to-Chip Interconnect

A new type of broadband link enabling extremely high-speed chip-to-chip communication is presented. The link is composed of fully integrated sub-mmWave on-chip traveling wave power couplers and a low-cost planar dielectric waveguide. This structure is based on a differentially driven half-mode substrate integrated waveguide supporting the first higher order hybrid microstrip mode. The cross-sectional width of the coupler structure is tapered in the direction of wave propagation to increase the coupling efficiency and maintain a large coupling bandwidth while minimizing its on-die size. A rectangular dielectric waveguide, constructed from Rogers Corporation R3006 material, is codesigned with the on-chip coupler structure to minimize coupling loss. The coupling structure achieves an average insertion loss of 4.8 dB from 220 to 270 GHz, with end-to-end link measurements presented. This system provides a packaging-friendly, cost effective, and high performance planar integration solution for ultrabroadband chip-to-chip communication utilizing millimeter waves.

Analysis of tunable Marchand baluns

The paper tackles the issue of designing tunable Marchand baluns and provides an insight on available approaches for integrating the structure in a semiconductor process. Limitation of the approach and possible solutions are also discussed. The analysis is applied to a Marchand balun fabricated in IBM 8HP SiGe process to demonstrate the feasibility of the approach. A mix of measured and simulated data is used to support the analysis at Q band. State-of-the-art performance is achieved.

Fabless design: Got any problem with that?

Summary form only given. The past decade has seen a tremendous growth in fabless design companies which have been able to offer new products in the communication and electronic application market without bearing the high costs associated with a manufacturing infrastructure. On the other hand, foundries have been able to meet that demand with a large range of Silicon processes - from low cost to high performance devices. This relationship has worked out very well in the entire semiconductor industry as new demand has been met by new faster devices; and new faster devices have enabled more integration and more complexity, making Silicon the first choice in areas that were dominated by compound semiconductors just a handful of years ago. Is this symbiotic relationship coming to an end or is it getting stronger? Moores law has paced the speed in device innovation so far, but now improvements are getting harder and harder to achieve - and the fabrication cost for fabless innovators is sky-rocketing. Access to the latest technology can be prohibitive for many design teams and process innovation is becoming an ever more expensive proposition. The foundry business is dominated by a few large companies, whose operation and choices may affect the whole world. Further, the technological knowledge concentrates where the fabs are located, consolidating the manufacturing business to a limited number of locations. Is there still room for fabless start-ups to grow in this environment? Is this business for big players only? Or should the small players just resign to considering a foundry a commodity, focus on integration of more and more functionality and passively observe how the technology evolves? Our panelist will take this discussion from here and they will give the audience new perspectives on what the future may bring to the fabless design industry.

Remembering Roger Pollard

With Dr. Roger Pollards passing on December 3rd, 2011, his friends and colleagues take this opportunity to look back and review his numerous contributions.