Luis A. Villa-Vargas

CMOS prototype vision chip with digital pixel structure for grey level image segmentation by means of thresholding and time multiplexing

In this article, a CMOS prototype vision chip with digital pixel structure for grey level image segmentation by means of thresholding and time multiplexing is presented. This approach splits scenes into m frames (one frame per grey level interval). One advantage about this design is that an analogue to digital converter is not required. Moreover, image acquisition and segmentation are performed at the same time by pixels that work simultaneously with each other. The performance from each pixel deals with a maximum quantum efficiency of 0.65, pixel size of 132 μm × 176 μm, fill factor of 0.78%, dark current of 15 mV/s, power dissipation per frame of 341 μW, minimum exposure time of 28.6 μs, maximum exposure time of 1.9 ms, random noise of 3 mV, optical dynamic range of 51 dB and majority of cells with 0–3% of mismatch. Scene decomposition into 256 images occurs in 30.5 ms with white illumination of 650 Lx.

A Feasible Genetic Optimization Strategy for Parametric Interval Type-2 Fuzzy Logic Systems

This paper presents an optimization strategy for interval type-2 fuzzy systems by using the conjunction operation called the (p)-monotone sum of t-norms. A direct-current servomotor control system is implemented to test the performance of the type-1, interval type-2 and interval type-2 fuzzy systems with parametric operations, under several noisy conditions. To rate them, a multi-objective fitness function, based on the main transient parameters, is proposed to ensure the genetic algorithm to find the best squared feedback signal, when a white noise signal with different amplitudes is added to the reference. In addition, the optimization strategy includes the parametric conjunction suppression to analyze how a rule-associated parametric conjunction directly influences on system performance. Such rule suppression can be used to reduce the number of parametric conjunction operations required to obtain an additional performance improvement. Experimental results of the servomotor control system show that parametric conjunctions used in the interval type-2 fuzzy logic system provide additional advantages over its nonparametric counterpart.

Association measures on the set of subintervals of [0,1]

The methods of construction of non-statistical association measures on the set of subintervals of [0,1] are proposed. These measures are defined as functions satisfying the properties generalizing properties of correlation coefficient. The proposed association measures can be extended on interval valued fuzzy sets and on interval valued intuitionistic fuzzy sets.

Hardware Design of Digital Parametric Conjunctors and t-Norms

Abstract This paper presents the hardware design and its implementation on FPGA of several parametric families of digital conjunctors and t-norms built from simple basic t-norms. The authors propose the method of unified presentation of the p-monotone sum, the simplified versions of the ordinal sum of t-norms and t-subnorms, and the method of extension of t-norms by the drastic t-norm. Such unification gives possibility to join several methods of construction of parametric digital conjunctors and t-norms in one scheme with the efficient FPGA implementation. The logic schemes of the proposed design are presented, and the comparative analysis of the latency time and the resources used for the implementation is given.

The Tellez-Molina-Villa algorithm

The Tellez-Molina-Villa (TMV) algorithm is a new defuzzification method for interval type-2 fuzzy systems. It is based on found the mean trajectory of any interval type-2 fuzzy set. With the mean trajectory we pretend to find the type-1 reduced fuzzy set of the interval type-2 fuzzy set. With this algorithm we try to find the generalized centroid of any interval type-2 fuzzy set. Also, we try to increase the type-2 fuzzy logic system accuracy. In general we found from 5 defuzzification methods that try to extract a crisp value from an interval type-2 fuzzy set as a representative value. First is necessary to obtain a type-1 fuzzy set from the type-2 fuzzy set, second from this reduced fuzzy set obtain a single crisp value. This crisp value represents lot of information, so that is necessary to do these steps carefully because we can obtain misinformation from the type-2 fuzzy inference system. In this paper we present some result from the new algorithm, and in order to compare the TMV algorithm we present comparative results with 5 type-2 defuzzification methods. From the obtained results we demonstrated that the TMV approach performs better that the Nie-Tan method. In fact, we can say that the TMV algorithm has at least equivalent results than Karnik-Mendel algorithm that in our opinion is one of the best defuzzification methods, but with the difference that the TMV algorithm is based on the mean trajectory of an interval type-2 fuzz set.

A compact CMOS Class-AB analog median filter

A power efficient implementation of a CMOS Class-AB analog median filter is presented. The median detector is based on transconductance comparators accomplished with new Differential Flipped Voltage Followers. The followers employ a current comparator to switch-on an auxiliary transistor to drive additional current whenever it is required, performing Class-AB operation. Area is saved by taking advantage of the large impedance node of the current comparator to accomplish Miller frequency compensation. Simulation results using the ON-SEMI 0.5 μm technology parameters validate the proposed structure.

A 90 µm × 64 µm 225 µW class-AB CMOS differential flipped voltage follower with output driving capability up to 100 pF

A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, 0.5@mm CMOS technology and the Pelgroms mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology.

A class-AB CMOS differential flipped voltage follower with output driving capability up to 100pF

A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, 0.5@mm CMOS technology and the Pelgroms mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology.

A 90µm×64µm225μW class-AB CMOS differential flipped voltage follower with output driving capability up to 100 pF

A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, 0.5@mm CMOS technology and the Pelgroms mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology.

Parametric t-norms in reconfigurable digital fuzzy systems

The problem of hardware implementation of parametric t-norms in reconfigurable fuzzy systems is discussed. Several parametric families of t-norms suitable for such implementation are considered. FPGA implementation of them is discussed.