Luiza de Macedo Mourelle

Swarm intelligent systems

Methodologies Based on Particle Swarm Intelligence.- Swarm Intelligence: Foundations, Perspectives and Applications.- Waves of Swarm Particles (WoSP).- Grammatical Swarm: A Variable-Length Particle Swarm Algorithm.- SWARMs of Self-Organizing Polymorphic Agents.- Experiences Using Particle Swarm Intelligence.- Swarm Intelligence - Searchers, Cleaners and Hunters.- Ant Colony Optimisation for Fast Modular Exponentiation using the Sliding Window Method.- Particle Swarm for Fuzzy Models Identification.- A Matlab Implementation of Swarm Intelligence based Methodology for Identification of Optimized Fuzzy Models.

Parallel evolutionary computations

Parallel Evolutionary Optimization.- A Model for Parallel Operators in Genetic Algorithms.- Parallel Evolutionary Multiobjective Optimization.- Parallel Hardware for Genetic Algorithms.- A Reconfigurable Parallel Hardware for Genetic Algorithms.- Reconfigurable Computing and Parallelism for Implementing and Accelerating Evolutionary Algorithms.- Distributed Evolutionary Computation.- Performance of Distributed GAs on DNA Fragment Assembly.- On Parallel Evolutionary Algorithms on the Computational Grid.- Parallel Evolutionary Algorithms on Consumer-Level Graphics Processing Unit.- Parallel Particle Swarm Optimization.- Intelligent Parallel Particle Swarm Optimization Algorithms.- Parallel Ant Colony Optimization for 3D Protein Structure Prediction using the HP Lattice Model.

Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic

Modular exponentiation is the cornerstone computation in public-key cryptography systems such as RSA cryptosystems. The operation is time consuming for large operands. This paper describes the characteristics of three architectures designed to implement modular exponentiation using the fast binary method: the first field-programmable gate array (FPGA) prototype has a sequential architecture, the second has a parallel architecture, and the third has a systolic array-based architecture. The paper compares the three prototypes as well as Blum and Paars implementation using the time times area classic factor. All three prototypes implement the modular multiplication using the popular Montgomery algorithm

Evolutionary Computation: from Genetic Algorithms to Genetic Programming

This chapter presented the biological motivation and fundamental aspects of evolutionary algorithms and its constituents, namely genetic algorithm, evolution strategies, evolutionary programming and genetic programming. Most popular variants of genetic programming are introduced. Important advantages of evolutionary computation while compared to classical optimization techniques are also discussed.

Multi-Objective Swarm Intelligent Systems

The editors of this volume, Nadia Nedjah, Leandro dos Santos Coelho and Luiza de Macedo Mourelle, have done a superb job of assembling some of the most innovative and intriguing applications and additions to the methodology and theory of multi-objective swarm intelligence the immitationof social swarms behaviors for the solution of optimization problems with respect tomany criteria.

Efficient Parallel Modular Exponentiation Algorithm

Modular exponentiation is fundamental to several public-key cryptography systems such as the RSA encryption system, as well as the most dominant part of the computation performed. The operation is time consuming for large operands. This paper analyses and compares the complexity of a variety of algorithms proposed to compute the modular exponentiation of a relatively large binary number, and proposes a new parallel modular exponentiation method.

Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization

Network-on-chips (NoC) is considered the next generation of communication infrastructure in embedded systems, which are omnipresent in different environments, such as cars, cell phones, and digital cameras. In the platform-based design methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. The selection of the most suited set of IPs as well as their physical mapping onto the NoC infrastructure to implement efficiently the application at hand are two hard combinatorial problems. In this paper, we propose the use of multi-objective evolutionary algorithms to perform the assignment and mapping stages of any given application on a customized NoC infrastructure. The resulting NoC platform is custom-cut for the application at hand. Only the actually used resources, switches and channels by the application mapping are part of the customized implementation platform. The optimization is driven by the minimization of required hardware area, the imposed execution time and the necessary power consumption of the final implementation, and yet avoiding hot spots.

Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs

Artificial neural networks (ANNs) is a well known bio-inspired model that simulates human brain capabilities such as learning and generalization. ANNs consist of a number of interconnected processing units, wherein each unit performs a weighted sum followed by the evaluation of a given activation function. The involved computation has a tremendous impact on the implementation efficiency. Existing hardware implementations of ANNs attempt to speed up the computational process. However these implementations require a huge silicon area that makes it almost impossible to fit within the resources available on a state-of-the-art FPGAs. In this paper, we devise a hardware architecture for ANNs that takes advantage of the dedicated adder blocks, commonly called MACs to compute both the weighted sum and the activation function. The proposed architecture requires a reduced silicon area considering the fact that the MACs come for free as these are FPGAs built-in cores. The hardware is as fast as existing ones as it is massively parallel. Besides, the proposed hardware can adjust itself on-the-fly to the user-defined topology of the neural network, with no extra configuration, which is a very nice characteristic in robot-like systems considering the possibility of the same hardware may be exploited in different tasks.

An efficient problem-independent hardware implementation of genetic algorithms

In this paper, we propose a massively parallel architecture for hardware implementation of genetic algorithms. This design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimise the required hardware area without much increase in response time. Last but not least, we demonstrate the characteristics of the proposed hardware and compare it to existing ones.

Fast Less Recursive Hardware for Large Number Multiplication Using Karatsuba-Ofman’s Algorithm

Multiplication of long integers is a cornerstone primitive in most cryptosystems. Multiplication for big numbers can be performed best using Karatsuba-Ofman’s divide-and-conquer approach. Multiplying long integers using Karatsuba-Ofman’s algorithm is fast but the algorithm is highly recursive. We propose a less recursive and efficient hardware architecture for this algorithm. We compare the proposed multiplier to other existing ones.