Lukasz Masko

Communication on the fly and program execution control in a system of dynamically configurable SMP clusters

New architectural solutions for parallel systems built of bus-based shared memory processor clusters are presented. A new paradigm is proposed for interprocessor communication, called communication on the fly. With this paradigm, processors can be dynamically switched between clusters at program run-time to bring in their caches data that can be read by many processors in a cluster at the same time they are written to the cluster memory. A cache controlled macro data flow program execution paradigm is also proposed. Programs are structured into tasks for which all required data are brought to the processor data cache before task execution. A. new graph representation of programs is introduced, which enables modeling of functioning of data caches, memories, bus arbiters, processor switching between clusters and parallel reads of data on the fly. This representation is used for realistic simulation of a numerical algorithm execution based on distribution of parallel tasks between dynamic SMP clusters and on communication on the fly. Performance evaluation results are presented for different configurations of the programs and shared memory clusters in the system.

Program Design Environment for Multicore Processor Systems with Program Execution Controlled by Global States Monitoring

A new distributed program graphical design environment is described in the paper. It is oriented towards designing program execution control based on a built-in system infrastructure which enables easy global application states monitoring in systems based on multicore processors. Two aspects of global application control design are covered. First is the global control flow in programs at the level of processes and threads. The second is the asynchronous control of internal process and thread behavior. The proposed control infrastructure is based on structural program elements called synchronizers organized at the process and thread levels to collect state information, evaluate control predicates on global states and send signals to application program threads and processes to stimulate global control actions. The paper presents principles of the application program graphical design and programming methods to implement global control at the level of threads.

Scheduling moldable tasks for dynamic SMP clusters in soc technology

The paper presents an algorithm for scheduling parallel programs for execution in a parallel architecture based on dynamic SMP processor clusters with data transfers on the fly. The algorithm is based on the concept of moldable computational tasks. First, an initial program graph is decomposed into sub–graphs, which are then treated as moldable tasks. So identified moldable tasks are then scheduled using an algorithm with warranted schedule length.

Atomic operations for task scheduling for systems based on communication on-the-fly between SMP clusters

Communication on-the-fly is a new, very efficient method of transferring data between shared memory processor clusters. It is based on synergy of processor switching between clusters and multiple reads of data from a transmission network shared by many processors. Effective use of this communication requires from the program to be specially structured. This paper presents a proposal of scheduling technique for programs given as Extended Macro-Dataflow Graphs. Scheduling is based on introducing proper transformations to the program graphs that reduce execution time of the program. These transformations work only on small subgraphs of the whole graph, but give global execution speedup. They are designed to use special architectural features such as communication on-the-fly and processor switching between clusters. Property of locality allows to preserve in every step the advantages of transformations applied to the graph earlier. The paper presents a set of such transformations. To show usefulness of them, an exemplary scheduling algorithm, which uses these transformations and an example of its application are presented.

A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters

The paper presents a new architectural solution for parallel systems built of shared memory processor clusters. The system is based on dynamically run-time reconfigurable multi-processor clusters; each organized around a local shared memory module placed in a common address space. Each memory module is accessed by a local cluster bus and a common inter-cluster bus. Programs are organized accordingly to their macro dataflow graphs in which tasks and communication are so defined, as to eliminate reloading of data caches during task execution. The behaviour of the proposed system has been evaluated by simulation based on an extended macro dataflow graph representation that includes modelling of data bus arbiters in the system. Program distribution into dynamic processor clusters assumes run-time switching of processors between busses and memory modules. It can reduce contention on data busses. CG algorithm execution in the proposed architecture shows seed-up greater than 4 when 5 busses are applied instead of one.

Program execution control for communication on the fly in dynamic shared memory processor clusters

The paper concerns efficient architectural solutions for shared memory systems composed of processor clusters based on busses. The essential proposed feature is program run-time dynamic switching of processors between clusters. A new communication paradigm, called communication on the fly is proposed, which is a combination of processor switching between clusters and parallel data reads of data from cluster busses to processor data caches. Specific data cache functionality is assumed in the system. Programs are decomposed into such tasks executed without preemption, so as to eliminate reloading of caches during task execution. A cache controlled program execution paradigm is proposed in which task execution is enabled only if all necessary data have been introduced to the processor data cache. An extended macro-data flow program graph representation is proposed for modeling functioning of data caches, data bus arbiters, switching processors between clusters and multiple parallel reads of data on the fly useful for designing parallel programs for execution in the proposed architecture. This new program representation has been used for simulated symbolic execution of an FFT program graph, based on mapping of parallel tasks on dynamic SMP clusters with communication on the fly.

Optimizing Distributed Data Mining Applications Based on Object Clustering Methods

The exponential computational cost involved in traditional data mining methods enforces search for less complex new algorithms. Especially, data mining on grid is a challenge due to the lack of shared memory in grid computing, which puts special attention to communication optimization. The aim of the DisDaMin project (distributed data mining), described in the paper, is solving data mining problems by using new distributed algorithms intented for execution in grid environments. The DisDaMin implements intelligent fragmentation of data by clustering methods and asynchronous collaborative processing adjusted to grid environments. The DG-ADAJ environment provides adaptive control of distributed applications written in Java for desktop grid. It constitutes a component-based middleware, which allows for optimized distribution of applications on clusters of Java virtual machines, monitoring of application execution and dynamic online balancing of processing and communication. The DG-ADAJ system provides a middleware platform for desktop grid that could be used as a deployment base for DisDaMin algorithms. In this paper, we propose static object placement optimization algorithms for fragmentation of data in the DisDaMin project. The algorithms use DG-ADAJs object clustering methods to provide optimized local processing on each node with minimized inter-node communication

Program graph scheduling for dynamic SMP clusters with communication on the fly

The paper concerns task graph scheduling in parallel programs for a parallel architecture based on dynamic SMP processor clusters with data transmissions on the fly. The assumed executive computer architecture consists of a set of NoC modules, each containing a set of processors and memory blocks connected via a local interconnection network. NoC modules are connected via a global interconnection network. An algorithm for scheduling parallel program graphs is presented, which decomposes an initial program graph into sub-graphs, which are then mapped to NoC modules, reducing global communication between modules. Then these subgraphs are structured inside the modules to include reads on the fly and processor switching. Reads on the fly reduce execution time of the program by elimination of read operations in linear program execution time.

Dynamic SMP clusters with communication on the fly

Efficient architectural solutions for systems based on shared memory processor clusters are presented in the paper. In the proposed architecture, processors can be dynamically switched between bus-based SMP clusters at program run-time. A switched processor can bring data in its cache that can be read on the fly by processors in the cluster when written into the cluster memory. This new inter-cluster data transfer paradigm is called communication on the fly. For execution in the proposed architecture, programs are structured accordingly to macro-data flow graphs in which task composition and communication are so defined, as to eliminate reloading of data caches during task execution. An extended macro-data flow graph representation is presented in the paper. It enables modeling of program execution control in the system including parallel task execution, data cache functioning, data bus arbiters, switching processors between clusters and multiple parallel reads of data on the fly. Simulation results for a very fine-grained parallel numerical example are presented.

Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly

This paper presents a new version of the dynamic SMP cluster -based architecture oriented towards networks on chip implementation technique. Smaller sub-networks with many dynamic SMP clusters and communication on the fly are connected by a central global network. Processors are provided with multi-ported data caches that enable parallel data transactions with memory modules, including parallel data pre-fetching and communication on the fly. Simulation experiments are described, based on a graph program representation and an automatic graph evaluator. They show efficiency of the proposed solution for very fine grain numerical problems.