Luping Li

Comparing Electron Recombination via Interfacial Modifications in Dye-Sensitized Solar Cells

Establishing a blocking layer between the interfaces of the photoanode is an effective approach to improve the performance of dye-sensitized solar cells (DSSCs). In this work, HfO2 blocking layers are deposited via atomic layer deposition (ALD) onto tin-doped indium oxide (ITO) and TiO2. In both cases, addition of the blocking layer increases cell efficiencies to greater than 7%. The improved performance for a HfO2 layer inserted between the ITO/TiO2 interface is associated with an energy barrier that reduces electron recombination. HfO2 blocking layers between the TiO2/dye interface show more complex behavior and are more sensitive to the number of ALD cycles. For thin blocking layers on TiO2, the improved device performance is attributed to the passivation of surface states in TiO2. A distinct transition in dark current and electron lifetime are observed after 4 ALD cycles. These changes to performance indicate thick HfO2 layers on TiO2 formed an energy barrier that significantly hinders cell performance.

Improving Performance via Blocking Layers in Dye-Sensitized Solar Cells Based on Nanowire Photoanodes.

Electron recombination in dye-sensitized solar cells (DSSCs) results in significant electron loss and performance degradation. However, the reduction of electron recombination via blocking layers in nanowire-based DSSCs has rarely been investigated. In this study, HfO2 or TiO2 blocking layers are deposited on nanowire surfaces via atomic layer deposition (ALD) to reduce electron recombination in nanowire-based DSSCs. The control cell consisting of ITO nanowires coated with a porous shell of TiO2 by TiCl4 treatment yields an efficiency of 2.82%. The efficiency increases dramatically to 5.38% upon the insertion of a 1.3 nm TiO2 compact layer between the nanowire surface and porous TiO2 shell. This efficiency enhancement implies that porous sol-gel coatings on nanowires (e.g., via TiCl4 treatment) result in significant electron recombination in nanowire-based DSSCs, while compact coatings formed by ALD are more advantageous because of their ability to act as a blocking layer. By comparing nanowire-based DSSCs with their nanoparticle-based counterparts, we find that the nanowire-based DSSCs suffer more severe electron recombination from ITO due to the much higher surface area exposed to the electrolyte. While the insertion of a high band gap compact layer of HfO2 between the interface of the conductive nanowire and TiO2 shell improves performance, a comparison of the cell performance between TiO2 and HfO2 compact layers indicates that charge collection is suppressed by the difference in energy states. Consequently, the use of high band gap materials at the interface of conductive nanowires and TiO2 is not recommended.

Fabricating vertically aligned sub-20 nm Si nanowire arrays by chemical etching and thermal oxidation

Silicon nanowires (SiNWs) are appealing building blocks in various applications, including photovoltaics, photonics, and sensors. Fabricating SiNW arrays with diameters <100 nm remains challenging through conventional top-down approaches. In this work, chemical etching and thermal oxidation are combined to fabricate vertically aligned, sub-20 nm SiNW arrays. Defect-free SiNWs with diameters between 95 and 200 nm are first fabricated by nanosphere (NS) lithography and chemical etching. The key aspects for defect-free SiNW fabrication are identified as: (1) achieving a high etching selectivity during NS size reduction; (2) retaining the circular NS shape with smooth sidewalls; and (3) using a directional metal deposition technique. SiNWs with identical spacing but variable diameters are demonstrated by changing the reactive ion etching power. The diameter of the SiNWs is reduced by thermal oxidation, where self-limiting oxidation is encountered after oxidizing the SiNWs at 950 °C for 1 h. A second oxidation is performed to achieve vertically aligned, sub-20 nm SiNW arrays. Si/SiO2 core/shell NWs are obtained before removing the oxidized shell. HRTEM imaging shows that the SiNWs have excellent crystallinity.

Tin-Doped Indium Oxide-Titania Core-Shell Nanostructures for Dye-Sensitized Solar Cells

Dye-sensitized solar cells (DSSCs) hold great promise in the pursuit of reliable and cheap renewable energy. In this work, tin-doped indium oxide (ITO)-TiO2 core-shell nanostructures are used as the photoanode for DSSCs. High-density, vertically aligned ITO nanowires are grown via a thermal evaporation method and TiO2 is coated on nanowire surfaces via TiCl4 treatment. It is found that high TiO2 annealing temperatures increase the crystallinity of TiO2 shell and suppress electron recombination in the core-shell nanostructures. High annealing temperatures also decrease dye loading. The highest efficiency of 3.39% is achieved at a TiO2 annealing temperature of 500°C. When HfO2 blocking layers are inserted between the core and shell of the nanowire, device efficiency is further increased to 5.83%, which is attributed to further suppression of electron recombination from ITO to the electrolyte. Open-circuit voltage decay (OCVD) measurements show that the electron lifetime increases by more than an order of magnitude upon HfO2 insertion. ITO-TiO2 core-shell nanostructures with HfO2 blocking layers are promising photoanodes for DSSCs.

Controlling the Geometries of Si nanowires through tunable nanosphere lithography

A tunable nanosphere lithography (NSL) technique is combined with metal-assisted etching of silicon (Si) to fabricate ordered, high-aspect-ratio Si nanowires. Non-close-packed structures are directly prepared via shear-induced ordering of the nanospheres. The spacing between the nanospheres is independent of their diameters and tuned by changing the loading of nanospheres. Nanowires with spacings between 110 and 850 nm are easily achieved with diameters between 100 and 550 nm. By eliminating plasma or heat treatment of the nanospheres, the diameter of the nanowires fabricated is nearly identical to the nanosphere diameter in the suspension. The elimination of this step helps avoid common drawbacks of traditional NSL approaches, leading to the high-fidelity, large-scale fabrication of highly crystalline, nonporous Si nanowires in ordered hexagonal patterns. The ability to simultaneously control the diameter and spacing makes the NSL technique more versatile and expands the range of geometries that can be fabricated by top-down approaches.

A facile route to prepare reflective counter electrode for enhanced dye-sensitised solar cell efficiency

Dye sensitised solar cells (DSSCs) represent a promising technology for the development of next-generation photovoltaics. The counter electrode in a DSSC typically consists of a tin-doped indium oxide (ITO) substrate covered by Pt as the catalyst. To increase DSSC efficiency and reduce fabrication cost, most existing methods involve multiple steps and are time consuming. In this work, we present a facile and low-cost alternative to prepare reflective counter electrodes for DSSCs with high efficiency. By simply sputtering a 30-nm-thick Pt film on ITO without further treatment, cell efficiency reached 7.08%, corresponding to an 11% increase from the control. Similar efficiency was achieved when a Pt film was sputtered on regular glass, which is a low-cost alternative to ITO. UV-vis spectroscopy showed that the reflectance for the control was below 30%, while the reflectance for the Pt-sputtered counter electrodes was above 70%, which is higher than the counter electrodes prepared by other methods.