Lutfi Albasha

Novel multimode J-pHEMT front-end architecture with power-control scheme for maximum efficiency

Based upon a unique junction pseudomorphic high electron-mobility transistor (J-pHEMT) device, a novel method of providing high-efficiency power amplifier (PA) power control for variable envelope modulation schemes is demonstrated for enhanced data rates for global system for mobile communications evolution and wide-band code division multiple access. This new technique, based upon the use of a linear PA, was extended to provide a simple, but highly effective method of PA efficiency enhancement based upon dynamic adaptive bias control. Together, the architecture allows for substantially higher efficiency levels compared with conventional linear solutions over the entire range of handset operating conditions, while avoiding the necessity for complex control loops and linearization schemes. Furthermore, it is shown that the characteristics of the J-pHEMT, when used with this architecture, can be exploited to facilitate an efficient and completely novel single-chip PA plus antenna switch to substantially reduce the RF complexity of a cellular handset.

A Low-Cost High-Performance Digital Radar Test Bed

This paper describes the design of a dual-channel S-band digital radar test bed. The test bed combines stretch processing with a novel and cost-effective hardware architecture that enables it to achieve an in-band dynamic range of 60 dB over 600 MHz of instantaneous bandwidth. The dual digital receiver channels allow for adaptive digital beamforming which can be used to mitigate a directional source of interference. Experimental test and verification results are presented to demonstrate system performance.

RF energy harvesting for autonomous wireless sensor networks

The system specifications of RF energy harvesting are outlined, indicating the general guideline of low power circuit and system design as well as the frequency set to be used in the system. Four frequency bands representing five wireless standards were chosen namely, GSM, DTV, Wi-Fi, Bluetooth and road tolling system. A harvesting system has been designed and simulated. A microstrip line antenna, RF-DC rectifier circuit and a voltage doubler circuit were designed. The simulations show promising preliminary results for the RF energy harvesting system compared to similar work in literature.

Investigation of RF Signal Energy Harvesting

The potential utilization of RF signals for DC power is experimentally investigated. The aim of the work is to investigate the levels of power that can be harvested from the air and processed to achieve levels of energy that are sufficient to charge up lowpower electronic circuits. The work presented shows field measurements from two selected regions: an urbanized hence signal congested area and a less populated one. An RF harvesting system has been specifically designed, built, and shown to successfully pick up enough energy to power up circuits. The work concludes that while RF harvesting was successful under certain conditions, however, it required the support of other energy harvesting techniques to replace a battery. Efficiency considerations have, hence, placed emphasis on comparing the developed harvester to other systems.

High-Resolution On-Chip

In this paper, an S-band radar system that uses stretch processing is developed at the chip level. The novelty in this paper lies in providing an integrated, compact and miniaturized high-performance S-band radar system chipset. The radar has many characteristics that ensure high performance: 1) a wide bandwidth signal (600 MHz) that provides high resolution to distinguish between close objects; 2) an usage of stretch processing, which dramatically reduces the required sampling rates and relaxes the specifications of analog-to-digital converters; 3) high dynamic range (58 dB) that allows weak signals to be detected from targets masked by the high levels of clutter (such as snow and rain); 4) multiple receiver channels that enable digital antenna beamforming at the receiver to mitigate any strong interferer; and 5) operation in the S-band (2-4 GHz) that provides high immunity against clutter in long range surveillance applications. The architecture study revealed a super-hetrodyne modulator and receiver architecture offered the best solution. The high-order filters were pushed off-chip to reduce silicon area, reduce power consumption, and improve filtering results. The circuit-level design focused on designing the receiver blocks. The design included a high linearity quad passive mixer, IF cascode and common source amplifiers, and a negative-gm voltage controlled oscillator. The total receiver system of the radar chipset was designed and simulated at the circuit level on IBM 180-nm CMOS technology. To the best knowledge of the authors, this is the first integrated and smallest high-performance S-band radar to be designed.

S

This paper investigates conductive concrete in electromagnetic shielding applications as a viable alternative to carbon-laced polyurethane, which is used as an absorber material in anechoic chambers. To greatly increase concrete’s electromagnetic shielding performance, carbon black, graphite powder, and steel fibers are introduced to its composition. Samples of conductive concrete have been prepared and its shielding effectiveness is evaluated. The test method is based on using power spectrum analysis to characterize the degree of shielding due to the different mechanisms of reflection and absorption. The tested samples are in the shape of anechoic chambers pyramidal cones, to provide gradual impedance gradient. Slabs with flat surface are also built and tested in order to compare the results. Measured data are then compared with published figures for commercial chamber performances. The range of frequency tested is from 1 to 5.5 GHz. The pyramidal conductive concrete samples yield an excellent shielding effectiveness of approximately 65 dB as opposed to the carbon-laced polyurethane performance of 50 dB.

-Band Radar System Using Stretch Processing

The design and measurements of a fabricated novel digitally programmable wideband power amplifier (PA) are presented. The PA is made suitable for use in all communication standards, including GSM, 3G, LTE and Femto-cells, offering a bandwidth of several octaves covering presently 300 MHz to 3.5 GHz. It meets power, efficiency and linearity specifications. The amplifier showed excellent performances. The uniquely linear and high power SONY GaAs J-PHEMT process along with novel output-stage multiple cascode topology structure are discussed. This enabled a distinctive larger output impedance and power and low voltage operation. The output stage offered 15-20 dB of gain without a driver. The circuit requires only little output or input matching for gain or impedance, depending on the application. In order to obtain higher gain and optimal application specific performance, a driver stage was added on the same die. A digitally programmable tuning chip was incorporated to the solution to optimize the performance for large bandwidths exceeding 40%. For smaller bandwidths no digital tuning was required. Digital pre-distortion algorithm was tested for better linearization. To the best knowledge of the authors, this is the first comprehensive plug-and-play solution for multi-band and multi-mode handset transmitters with the single chip one PA.

Feasibility Study of Using Electrically Conductive Concrete for Electromagnetic Shielding Applications as a Substitute for Carbon-Laced Polyurethane Absorbers in Anechoic Chambers

This paper proposes the realization of a three box parallel nonlinear model for predistorting a switched mode power amplifier (PA). Such amplifiers are highly efficient but exhibit very strong nonlinear effects, and this constraint has considerably limited their use. Through the implementation of accurate models as the predistorter, the nonlinearity inherent in the switched mode power amplifier can be compensated for. Driven by a wideband signal, simulations show that the model used achieves an improvement of 1.224dB in the adjacent channel power ratio (ACPR). Overall, the PA maintains 71.3% power added efficiency (PAE), a significant increase over other classes.

An Ultra-Wideband Digitally Programmable Power Amplifier With Efficiency Enhancement for Cellular and Emerging Wireless Communication Standards

In this article, the design and measurement details of a wideband low-noise amplifier (LNA) are presented. The LNA was successfully designed to operate over very high and ultra high frequency (VHF and UHF) ranges according to Digital TV (DVB-T) specifications. The novelty of the design lies in the achievement of low noise figure (NF) and high reverse isolation level across a wide bandwidth despite the resistive feedback topology. The latter was required in order to integrate the front-end block with a direct-conversion receiver. A measured large-signal compression point of P1dB = −10 dBm and a small-signal gain of 16 dB with gain flatness of <1 dB ripple, have all met commercial specifications tested over corners. The NF achieved was better than that specified and was less than 2 dB across the bandwidth. This front-end block was implemented in a commercial 0.25 μm Si BiCMOS process (f T = 20 GHz). The article discusses the measurement uncertainties imposed by the wide bandwidth, particularly in NF measurements, and the techniques adopted in this work to mitigate the errors imposed.

Switched mode power amplifier linearization using digital predistortion

This paper presents a low power wireless capacitive based CMOS humidity sensor to be used in Internet of Things (IoT)applications, powered through inductive coupling. The sensing element is implemented in standard CMOS technology with minimum post processing step. This sensor is based on the detection of change in frequency due to the change in humidity levels. The proposed humidity sensor is designed in 0.18μm Global Foundries process. The simulated results show that even a change of as small as 50fF in the sensing element is detected, indicating high sensitivity. This chip consumes around 600μW of total power at 1.5V.