Lynn Choi

Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture

A Compiler Framework for Supporting Speculative Multicore Processors.- Power-Efficient Heterogeneous Multicore Technology for Digital Convergence.- StarDBT: An Efficient Multi-platform Dynamic Binary Translation System.- Unbiased Branches: An Open Problem.- An Online Profile Guided Optimization Approach for Speculative Parallel Threading.- Entropy-Based Profile Characterization and Classification for Automatic Profile Management.- Laplace Transformation on the FT64 Stream Processor.- Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation.- Evolution of NAND Flash Memory Interface.- FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.- Exploiting Single-Usage for Effective Memory Management.- An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.- An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems.- Optimal Placement of Frequently Accessed IPs in Mesh NoCs.- An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips.- Performance of Keyword Connection Algorithm in Nested Mobility Networks.- Leakage Energy Reduction in Cache Memory by Software Self-invalidation.- Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters.- Runtime Performance Projection Model for Dynamic Power Management.- A Power-Aware Alternative for the Perceptron Branch Predictor.- Power Consumption and Performance Analysis of 3D NoCs.- A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels.- Bipartition Architecture for Low Power JPEG Huffman Decoder.- A SWP Specification for Sequential Image Processing Algorithms.- A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision.- FPGA-Accelerated Active Shape Model for Real-Time People Tracking.- Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures.- Synchronization Mechanisms on Modern Multi-core Architectures.- Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.- Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks.- Open Issues in MPI Implementation.- Implicit Transactional Memory in Kilo-Instruction Multiprocessors.- Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.- A Bypass Mechanism to Enhance Branch Predictor for SMT Processors.- Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor.- Architectural Solution to Object-Oriented Programming.

AMAC: Traffic-Adaptive Sensor Network MAC Protocol through Variable Duty-Cycle Operations

Sensor network MAC protocols usually employ periodic sleep and wakeup, achieving low duty-cycle to save energy and to increase the lifetime of battery-powered sensor devices. However, existing protocols require all the sensor nodes to operate on the same static schedule, waking up all the nodes at the same fixed interval periodically. This paper proposes a new media access control protocol called AMAC that can achieve significant energy savings by dynamically changing the schedule of each node depending on the traffic. In AMAC, each node can adjust the duration of the periodic interval as well as the duration of the active period depending on the traffic. Thus, busy nodes can operate with a high duty-cycle while idle nodes can operate with a low duty-cycle at the same time, achieving both low-energy and high-performance. The results of our detailed simulations confirm that AMAC can reduce the average energy consumption by a factor of up to 6.8 compared to an existing fixed duty-cycle MAC protocol while it can also improve the network performance for burst traffic patterns.

Characterization and modeling of a new via structure in multilayered printed circuit boards

We demonstrate that structure engineering of the transmission line near the via can reduce the amount of reflection of the RF signal. We have fabricated two types of vias with different transmission line geometries and have measured the reflection. The measured results show that the shape of the transmission line near the via hole is important in determining the total reflection of the via structure. The amount of reflection obtained from full three-dimensional (3-D) electromagnetic simulations can reproduce the measured results with reasonable accuracy, which suggests that efficient design of the via structure could be possible without resorting to hardware fabrication and characterization.

Low-Cost Application-Aware DVFS for Multi-core Architecture

As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay2 Product (ED2P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6% and 54.3% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED2P, our proposed technique reduces 36.4% and 14.7% of ED2P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.

DAG-based multipath routing for mobile sensor networks

We propose a new multipath routing protocol called DMR for mobile sensor networks, where any node can move anytime. DMR is based on the IETF RPL framework, which uses directed acyclic graph (DAG) to remove routing cycles. By broadcasting DAG construction messages including rank and link quality indication, DMR constructs DAG and provides path redundancy. This allows mobile sensors to find multiple alternative paths easily on local and global route failures. Our experimental results show that DMR successfully delivers more than 97% of messages while improving the energy efficiency for MSN by effectively reducing routing overheads by 65% and 56% on average compared to the existing MANET routing protocols AODV and AOMDV, respectively.

SPEED-MAC: Speedy and Energy Efficient Data Delivery MAC Protocol for Real-Time Sensor Network Applications

In this paper we consider the design of MAC protocol for real-time sensor network applications. Although existing wakeup scheduling techniques suggest end-to-end delay guarantees for such applications, their fixed wakeup schedules may not meet such constraints when multiple sensors compete for the event delivery at the same time. We propose a new MAC protocol called SPEED-MAC that can provide real-time delay guarantees with much lower energy consumption for both single-source and multi-source events. The main ideas underlying the protocol are two-fold. First, we introduce a novel wakeup technique called signaling wakeup period, which is small enough to detect collisions and contentions. By employing the signaling wakeup we can minimize the event report latency as well as the idle listening. Second, to resolve the collisions and contentions incurred by multi-source events, the protocol employs adaptive wakeups that combines static scheduling with contention-based media access control depending on the type of traffic. Our simulation results show that SPEED-MAC can achieve an order of magnitude energy savings while providing near optimal latency compared to the existing solutions.

Scalable packet classification through rulebase partitioning using the maximum entropy hashing

In this paper, we introduce a new packet classification algorithm, which can substantially improve the performance of a classifier. The algorithm is built on the observation that a given packet matches only a few rules even in large classifiers, which suggests that most of rules are independent in any given rulebase. The algorithm hierarchically partitions the rulebase into smaller independent subrulebases based on hashing. By using the same hash key used in the partitioning a classifier only needs to look up the relevant subrulebase to which an incoming packet belongs. For an optimal partitioning of rulebases, we apply the notion of maximum entropy to the hash key selection. We performed the detailed simulations of our proposed algorithm on synthetic rulebases of size 1 K to 500 K entries using real-life packet traces. The results show that the algorithm can significantly outperform existing classifiers by reducing the size of a rulebase by more than four orders of magnitude with just two-levels of partitioning. Both the time complexity and the space complexity of the algorithm exhibit linearity in terms of the size of a rulebase. This suggests that the algorithm can be a good scalable solution for medium to large rulebases.

M-MAC: Mobility-Based Link Management Protocol for Mobile Sensor Networks

In wireless sensor networks with mobile sensors, frequent link failures caused by node mobility generate wasteful retransmissions, resulting in increased energy consumption and decreased network performance. In this paper we propose a new link management protocol called M-MAC that can dynamically measure and predict the link quality. Based on the projected link status information each node may drop, relay, or selectively forward a packet, avoiding unnecessary retransmissions. Our simulation results show that M-MAC can effectively reduce the per-node energy consumption by as much as 25.8% while improving the network performance compared to a traditional sensor network MAC protocol in the case of both low and high mobility scenarios.

Virtual sink rotation: low-energy scalable routing protocol for ubiquitous sensor networks

In this paper we propose a new routing protocol called virtual sink rotation (VSR) routing for large-scale sensor networks. VSR can efficiently handle a large number of sources as well as a large number of sinks with potential mobility. Each sensor node is not required to know the global network topology nor the location awareness. The main ideas underlying the VSR are two folds. First, to alleviate the frequent location updates associated with multiple mobile sinks, the algorithm introduces a virtual sink, which acts as a data collection and dissemination center to collect the data from all the sources and forward them to the actual sinks. This virtual sink can easily support multiple sinks as well as the mobility of the sinks. Second, to address the excessive energy consumption among the sensor nodes around a sink, VSR employs virtual sink rotation, which distributes the role of the virtual sink over all the participating sensor nodes, thus achieving a uniform energy distribution across the entire sensor field and prolonging the lifetime of the network. Experimentation results confirm that the VSR routing can significantly save energy while it can also reduce both the message delay and the message delivery failures compared to previous schemes.

Compiler analysis for cache coherence: interprocedural array data-flow analysis and its impact on cache performance

In this paper, we present compiler algorithms for detecting references to stale data in shared-memory multiprocessors. The algorithm consists of two key analysis techniques, state reference detection and locality preserving analysis. While the stale reference detection finds the memory reference patterns that may violate cache coherence, the locality preserving analysis minimizes the number of such stale references by analyzing both temporal and spatial reuses. By computing the regions referenced by arrays inside loops, we extend the previous scalar algorithms for more precise analysis. We develop a full interprocedural array data-flow algorithm, which performs both bottom-up side-effect analysis and top-down context analysis on the procedure call graph to further exploit locality across procedure boundaries. The interprocedural algorithm eliminates cache invalidations at procedure boundaries, which were assumed in the previous compiler algorithms. We have fully implemented the algorithm in the Polaris parallelizing compiler. Using execution-driven simulations on Perfect Club benchmarks, we demonstrate how unnecessary cache misses can be eliminated by the automatic stale reference detection. The algorithm can be used to implement cache coherence in the shared-memory multiprocessors that do not have hardware directories, such as Cray T3D.