M A F van den Boogaart

Fabrication and application of a full wafer size micro/nanostencil for multiple length-scale surface patterning

A tool and method for flexible and rapid surface patterning technique beyond lithography based on high-resolution shadow mask method, or nanostencil, is presented. This new type of miniaturized shadow mask is fabricated by a combination of MEMS processes and focused ion beam (FIB) milling. Thereby apertures in a 100-500 nm thick low-stress silicon nitride membrane in the size range from 100 µm were made. The stencil device is mechanically fixed on the surface and used as miniature shadow mask during deposition of metal layers. Using this method, aluminum Micro- and nanostructures as small as 100 nm in width were patterned. The deposited Micro- and nano-scale structures were used as etch mask and transferred into a sub-layer (in our case silicon nitride) by dry plasma etching. High-resolution shadow masking can be used to create micro/nanoscale patterns on arbitrary substrates including mechanically fragile or chemically active surfaces.

Metallic Nanowires by Full Wafer Stencil Lithography

Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 mum long have been achieved showing a resistivity of 10 microOmegacm for Al and 5 microOmegacm for Au and maximum current density of approximately 10(8) A/cm(2). This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale.

A Compact and Low-Power CMOS Circuit for Fully Integrated NEMS Resonators

This brief presents a fully integrated nanoelectromechanical system (NEMS) resonator, operable at frequencies in the megahertz range, together with a compact built-in CMOS interfacing circuitry. The proposed low-power second-generation current conveyor circuit allows detailed read-out of the nanocantilever structure for either extraction of equivalent circuit models or comparative studies at different pressure and dc biasing conditions. In this sense, extensive experimental results are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing by nanostencil lithography. The proposed read-out scheme can be easily adapted to operate the nanocantilever in closed loop operation as a stand-alone NEMS oscillator

Permalloy thin films exchange coupled to arrays of cobalt islands

Periodic arrays of elongated cobalt islands exchange coupled to continuous Permalloy thin films were fabricated using silicon nitride stencil masks and the magnetic spin configurations during magnetization reversal were studied with photoemission electron microscopy. The presence of cobalt islands results in a spatial modulation of the magnetic properties of the Permalloy films and domain walls positioned at the island boundaries. While magneto-optical Kerr effect measurements indicate differences depending on film thickness, the direct observations reveal two reversal mechanisms: formation of domains running between the islands and coherent rotation followed by propagation of a large domain.

Silicon-Supported Membranes for Improved Large-Area and High-Density Micro/Nanostencil Lithography

In this paper, the fabrication and use of stencils for full-wafer scale shadow mask (stencil) lithography is described. The stencils fabricated via microelectromechanical systems are mechanically stabilized and show clearly reduced stress-induced membrane deformation, which translates into a more accurate surface pattern definition. Solid-state SiN membranes 500 nm thick and up to 1 mm2 in size having a 20-mum-thick silicon support rim following the outline of the stencil apertures were fabricated in a 100-mm Si wafer. The minimum aperture size presented in this paper is 3 mum. The increase of membrane stability was confirmed by depositing a highly stressed 35-nm-thick chrome layer. The results demonstrate a stability increase of the Si-supported compared to nonsupported membrane with identical shape by up to 89% as measured by the reduced out-of-plane deflection of overhanging membrane sections. Comparison by scanning electron microscopy and atomic force microscopy of the resulting micropatterns obtained by Cr deposition through both unsupported and Si-rim supported stencils shows better edge sharpness and clearer spatial details for surface patterns deposited through the stabilized stencil compared to those deposited through the nonsupported stencil. The improved stabilized stencils allow for large-area high-density surface patterning while maintaining membrane stability and pattern definition during stencil lithography

Full wafer integration of NEMS on CMOS by nanostencil lithography

Wafer scale nanostencil lithography is used to define 200 nm scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of ~2000 nano-devices by post-processing standard CMOS wafers using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies around 1.5 MHz were measured in air and vacuum and tuned by applying dc voltages of 10V and 1V respectively

Application of Microstencil Lithography on Polymer Surfaces for Microfluidic Systems with Integrated Microelectrodes

Microstencil lithography, a resistless, single-step direct vacuum patterning method, is one of promising methods for metal micropattern definition on polymer substrates that are not suitable for conventional photolithography. We propose to apply microstencil lithography to fabricate microelectrodes on flat and pre-structured polymer substrates which form parts of microfluidic systems with incorporated microelectrodes. However, microstencil lithography is accompanied by two main issues when considered as a low-cost, reproducible alternative to standard photolithography on polymer substrates: clogging and blurring. The clogging of stencil apertures induced by metal evaporation was checked in detail, and it was determined that approximately 50 % of the thickness of the evaporated metals was deposited at the side walls of the stencil apertures. The influence of gap presence on the deposited structures was also analyzed experimentally, and we quantified the pattern blurring

Sub-100 nm-scale aluminum nanowires by stencil lithography: Fabrication and characterization

We present the fabrication process and electrical characterization of sub-100 nm scale Al nanowires (NWs) fabricated by stencil lithography (SL). We use a stencil with sub- 100 nm wide nanoslits patterned by focused ion beam (FIB) milling. The stencil is aligned and clamped onto a substrate containing predefined electrical contacts. Then a 60 nm-thick layer of Aluminum (Al) is deposited through the stencil producing NWs with lengths of ~1, 2 and 5 mum and widths down to 65 nm. The NWs show an ohmic behavior with values varying from 30 Omega up to 300 Omega, depending on the dimensions of the structures. We have extracted a resistivity for the Al NWs of ~10 x 10-8 Omegam. We also show that stencils can be cleaned and reused, proving that SL is a cost-efficient and scalable manufacturing method for the direct fabrication of metallic NWs on a full wafer scale.

Computational Design and Optimisation of Mechanically Reinforced Masks for Stencil Lithography

Identifying, predicting and optimising stencil lithography is critical to the successful and timely development of this technique with a wide range of potential applications such as deposition on non- conventional and unstable materials (i.e. bio-chemical, hydrophobic), patterning heterostructures (epitaxial, magnetic, complex oxides, piezoelectric materials) and deposition of nanodevices onto CMOS. Previously confirmed for cantilever-like stencils is the thesis that degrading effects of stress-induced deformation of stencils can be overcome by strategic placement of corrugating structures. This approach is further exploited in this work to mechanically stabilise complex stencil designs. This involved studying the evolution of stencil deformation due to deposition induced stress and iterative design of optimal corrugation structures to be incorporated into the stencils. It is shown that degrading effects of stress-induced deformation of stencils can be significantly reduced which subsequently improves pattern definition. Reduction in deformation and in pattern distortion in the range of 50% to 96% was achieved.

Towards Reliable 100-Nanometer Scale Stencil Lithography on Fullwafer: Progress and Challenges

We have fabricated new and robust nanostencil membranes for the surface patterning of 100-nm scale Al wires on full wafer scale. The stencil membranes are mechanically reinforced with corrugations, making them more stable against accumulated stress. The apertures in the stencil are fabricated by a combination of UV lithography and focused ion beam milling, ranging from sub-100 nm to several microns. The presence of a gap between the stencil aperture and the substrate results in a blurring of the pattern, on the order of 100-300 nm. A gentle Al dry etch is applied to reduce the blurring, achieving sub-100 nm wide structures. 80 nm wide nanowires connected to micrometer-scale contact pads are fabricated and shown. The clogging of the stencil apertures is quantified and a cleaning procedure is presented.