M.A. Hasan

A modified Massey-Omura parallel multiplier for a class of finite fields

A Massey-Omura parallel multiplier of finite fields GF(2/sup m/) contains m identical blocks whose inputs are cyclically shifted versions of one another. It is shown that for fields GF(2/sup m/) generated by irreducible all one polynomials, a portion of the block is independent of the input cyclic shift; hence, the multiplier contains redundancy. By removing the redundancy, a modified parallel multiplier is presented which is modular and has a lower circuit complexity. >

Modular construction of low complexity parallel multipliers for a class of finite fields GF(2/sup m/)

Structures for parallel multipliers of a class of fields GF(2/sup m/) based on irreducible all one polynomials (AOP) and equally spaced polynomials (ESP) are presented. The structures are simple and modular, which is important for hardware realization. Relationships between an irreducible AOP and the corresponding irreducible ESPs have been exploited to construct ESP-based multipliers of large fields by a regular expansion of the basic modules of the AOP-based multiplier of a small field. Some features of the structures also enable a fast implementation of squaring and multiplication algorithms and therefore make fast exponentiation and inversion possible. It is shown that, if for a certain degree, an irreducible AOP as well as an irreducible ESP exist, then from the complexity point of view, it is advantageous to use the ESP-based parallel multiplier. >

High-Performance Architecture of Elliptic Curve Scalar Multiplication

A high performance architecture of elliptic curve scalar multiplication based on the Montgomery ladder method over finite field GF(2m) is proposed. A pseudo-pipelined word serial finite field multiplier with word size w, suitable for the scalar multiplication is also developed. Implemented in hardware, this system performs a scalar multiplication in approximately 6lceilm/wrceil(m-1) clock cycles and the gate delay in the critical path is equal to TAND + lceillog2(w/k)rceilTXOR, where TAND and TXOR are delays due to two-input AND and XOR gates respectively and 1 les k Lt w is used to shorten the critical path.

A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields

Based on Toeplitz matrix-vector products and coordinate transformation techniques, we present a new scheme for subquadratic space complexity parallel multiplication in GF(2n) using the shifted polynomial basis. Both the space complexity and the asymptotic gate delay of the proposed multiplier are better than those of the best existing subquadratic space complexity parallel multipliers. For example, with n being a power of 2, the space complexity is about 8 percent better, while the asymptotic gate delay is about 33 percent better, respectively. Another advantage of the proposed matrix-vector product approach is that it can also be used to design subquadratic space complexity polynomial, dual, weakly dual, and triangular basis parallel multipliers. To the best of our knowledge, this is the first time that subquadratic space complexity parallel multipliers are proposed for dual, weakly dual, and triangular bases. A recursive design algorithm is also proposed for efficient construction of the proposed subquadratic space complexity multipliers. This design algorithm can be modified for the construction of most of the subquadratic space complexity multipliers previously reported in the literature

Bit-serial systolic divider and multiplier for finite fields GF(2/sup m/)

A systolic structure for bit-serial division over the field GF(2/sup m/) is developed. Consideration is given to avoid global data communications and dependency of the time step duration on m. This is important for applications where the value of m is large. The divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m/sup 2/ and m, respectively. It does not depend on the irreducible polynomial and can be expanded easily. Moreover, with m additional simple processors, a bit-serial systolic multiplier is developed which uses part of the divider structure. This is advantageous from the implementation point of view, as both the divider and multiplier can be fabricated on a single chip, resulting in a reduction of area. >

A New Finite-Field Multiplier Using Redundant Representation

This article presents simple and highly regular architectures for finite field multipliers using a redundant representation. The basic idea is to embed a finite field into a cyclotomic ring which is based on the elegant multiplicative structure of a cyclic group. One important feature of our architectures is that they provide area-time trade-offs which enable us to implement the multipliers in a partial-parallel/hybrid fashion. This hybrid architecture has great significance in its VLSI implementation in very large fields. The squaring operation using the redundant representation is simply a permutation of the coordinates. It is shown that, when there is an optimal normal basis, the proposed bit-serial and hybrid multiplier architectures have very low space complexity. Constant multiplication is also considered and is shown to have an advantage in using the redundant representation.

Architecture for a low complexity rate-adaptive Reed-Solomon encoder

Multiple error-correcting Reed-Solomon (RS) codes have many practical applications. The complexity of an RS encoder depends on multiplications in the finite field over which the code is defined. We consider a triangular basis for representing the field elements, and present an architecture for a rate-adaptive RS encoder using a triangular basis multiplication algorithm. The architecture supports pipeline and bit-serial operations, and has a low circuit complexity. >

Low complexity word-level sequential normal basis multipliers

For efficient hardware implementation of finite field arithmetic units, the use of a normal basis is advantageous. In this paper, two classes of architectures for multipliers over the finite field GF(2/sup m/) are proposed. These multipliers are of sequential type, i.e., after receiving the coordinates of the two input field elements, they go through k, 1 /spl les/ k /spl les/ m, iterations (i.e., clock cycles) to finally yield all the coordinates of the product in parallel. The value of k depends on the word size w = /spl lceil/m/k/spl rceil/. For w > 1, these multipliers are highly area efficient and require fewer number of logic gates even when compared with the most area efficient multipliers available in the open literature. This makes the proposed multipliers suitable for applications where the value of m is large but space is of concern, e.g., resource constrained cryptographic systems. Additionally, if the field dimension m is composite, i.e., m = kn, then the extension of one class of the architectures yields a highly efficient multiplier over composite fields.

Low complexity bit-parallel multipliers for a class of finite fields

This short paper summarizes our recent results on construction of low-complexity bit-parallel finite field multiplier using polynomial basis. The complexity and time delay of the proposed multipliers are lower than those of the similar proposals.

Fault Detection Architectures for Field Multiplication Using Polynomial Bases

In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field