M. Bogdan

A Search for Microwave Emission From Ultra-High Energy Cosmic Rays

We present a search for microwave emission from air showers induced by ultrahigh energy cosmic rays with the microwave detection of air showers experiment. No events were found, ruling out a wide range of power flux and coherence of the putative emission, including those suggested by recent laboratory measurements.

The MIDAS telescope for microwave detection of ultra-high energy cosmic rays

Abstract We present the design, implementation and data taking performance of the MIcrowave Detection of Air Showers (MIDAS) experiment, a large field of view imaging telescope designed to detect microwave radiation from extensive air showers induced by ultra-high energy cosmic rays. This novel technique may bring a tenfold increase in detector duty cycle when compared to the standard fluorescence technique based on detection of ultraviolet photons. The MIDAS telescope consists of a 4.5xa0m diameter dish with a 53-pixel receiver camera, instrumented with feed horns operating in the commercial extended C-Band (3.4–4.2xa0GHz). A self-trigger capability is implemented in the digital electronics. The main objectives of this first prototype of the MIDAS telescope – to validate the telescope design, and to demonstrate a large detector duty cycle – were successfully accomplished in a dedicated data taking run at the University of Chicago campus prior to installation at the Pierre Auger Observatory.

The AMchip04 and the processing unit prototype for the FastTracker

Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment`s complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive event selection. We present the first prototype of a new Processing Unit (PU), the core of the FastTracker processor (FTK). FTK is a real time tracking device for the ATLAS experiment`s trigger upgrade. The computing power of the PU is such that a few hundred of them will be able to reconstruct all the tracks with transverse momentum above 1 GeV/c in ATLAS events up to Phase II instantaneous luminosities (3 × 1034 cm−2 s−1) with an event input rate of 100 kHz and a latency below a hundred microseconds. The PU provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the ``combinatorial challenge, is solved by the Associative Memory (AM) technology exploiting parallelism to the maximum extent; it compares the event to all pre-calculated ``expectations or ``patterns (pattern matching) simultaneously, looking for candidate tracks called ``roads. This approach reduces to a linear behavior the typical exponential complexity of the CPU based algorithms. Pattern recognition is completed by the time data are loaded into the AM devices. We report on the design of the first Processing Unit prototypes. The design had to address the most challenging aspects of this technology: a huge number of detector clusters (``hits) must be distributed at high rate with very large fan-out to all patterns (10 Million patterns will be located on 128 chips placed on a single board) and a huge number of roads must be collected and sent back to the FTK post-pattern-recognition functions. A network of high speed serial links is used to solve the data distribution problem.

ATLAS FTK: Fast Track Trigger

A track reconstruction system for the trigger of the ATLAS detector at the Large Hadron Collider is described. The Fast Tracker is a highly parallel hardware system designed to operate at the Level-1 trigger output rate. It will provide high-quality tracks reconstructed over the entire inner detector by the start of processing in the Level-2 trigger. The system is based on associative memories for pattern recognition and fast FPGA’s for track reconstruction. Its design and expected performance under instantaneous luminosities up to 3 10 34 =cm 2 =s are discussed.

FTK: a Fast Track Trigger for ATLAS

We describe the design and expected performance of a the Fast Tracker Trigger (FTK) system for the ATLAS detector at the Large Hadron Collider. The FTK is a highly parallel hardware system designed to operate at the Level 1 trigger output rate. It is designed to provide global tracks reconstructed in the inner detector with resolution comparable to the full offline reconstruction as input of the Level 2 trigger processing. The hardware system is based on associative memories for pattern recognition and fast FPGAs for track reconstruction. The FTK is expected to dramatically improve the performance of track based isolation and b-tagging with little to no dependencies of pile-up interactions.

Dual method of configuring Altera 10K family PLDS

A dual method of configuring programmable logic devices from the Altera FLEX 10K family is presented. A passive serial configuration is employed with the programming object files transferred from an onboard EPROM. The second source, selectable with a switch, is an external PC via a BitBlaster connection. Presently, Altera has no recommendation for a switchable source of programming files. The scheme presented has been tested on several configurations of single and multiple daisy-chained devices. This method enables field programmability together with EPROM power-up configuration for 10K devices. It proved to be a valuable tool during the debugging stage.

Enhancement of the ATLAS trigger system with a hardware tracker finder FTK

The existing three-level ATLAS trigger system is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to ~ 200 Hz for permanent storage at the LHC design luminosity of 1034 cm−2 s−1. When the LHC exceeds the design luminosity, the load on the Level-2 trigger system will significantly increase due both to the need for more sophisticated algorithms to suppress background and the larger event sizes. The Fast Tracker is a proposed upgrade to the current ATLAS trigger system that will operate at the full Level-1 accepted rate of 100 kHz and provide high quality tracks at the beginning of processing in the Level-2 trigger, by performing track reconstruction in hardware with massive parallelism of associative memories. The concept design is being advanced and justified with the performance in important physics areas, b-tagging, τ-tagging and lepton isolation. The prototyping with current technology is underway and R&D with new technologies has been started.