M.D. Robertson

Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon

In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25_μm pixel size prepared on top of a three transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

Determination of the size, shape, and composition of indium-flushed self-assembled quantum dots by transmission electron microscopy

Single and multiple layers of self-assembled InAs quantum dots (QDs) produced by the indium-flush technique have been studied by transmission electron microscopy (TEM) in an effort to develop techn ...

Families of islands in InAs/InP self-assembled quantum dots: a census obtained from magneto-photoluminescence

The low temperature photoluminescence properties of InAs/InP self-assembled quantum dots are investigated in magnetic fields up to 17 T. The zero field spectrum exhibits a number of inhomogeneously broadened peaks similar to the highly excited spectrum of InAs/GaAs quantum dots in which emission from excited states can be observed. However, for InAs/InP dots, application of a magnetic field in the Faraday configuration reveals only weak diamagnetic shifts, thus proving that the transitions originate from zero angular momentum states consistent with ground state emission from distinct families of islands present in the sample. The diamagnetic shift is observed to increase as the thickness of the island family increases. Calculations performed assuming a flat disc geometry show that the latter effect can be accounted for by the change in carrier effective mass as the dot thickness increases.

Determination of elastic strains in epitaxial layers by HREM

Abstract A new technique is presented to directly measure strains in epitaxial systems from high-resolution electron microscope (HREM) images. This method involves the calculation of the cumulative sum (CUSUM) of deviations from an average lattice fringe spacing value. Even when the variation in individual lattice fringe spacings is large compared to the difference in fringe spacing due to strain, the CUSUM method is capable of providing reliable strain determinations. The CUSUM approach was applied to three samples of semiconductor In 1−x Al x Sb/InSb (0≤x≤0.5) bilayer and superlattice systems in [11¯0] zone-axis projection. It was found that the epitaxial strains obtained from the HREM CUSUM method agreed with the bulk X-ray diffraction values when the sample thicknesses were on the order of 80–100 nm. Thinner specimens, on the order of 10–20 nm, displayed significant surface relaxation effects.

Asymmetric strain in nanoscale patterned strained -Si/strained -Ge/strained-Si heterostructures on insulator

The engineering of asymmetric strain is demonstrated in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructure on insulator with body thickness of 15nm. Starting material has layers with symmetric in-plane strain, including biaxial strained Si (∼1.8%, tension) and biaxial strained Ge (∼1.8%, compression). Micro-Raman spectroscopy is utilized to characterize the stress in heterostructures patterned into 10-μm-long bars with widths ranging from 300to30nm. Raman measurements are consistent with the transformation from biaxial to uniaxial compressive strain in the Ge for 30-nm-wide bars, as predicated by simulations. Measurements also demonstrate enhanced asymmetric relaxation in the tensile strained Si cap as its thickness is increased.

Ultrahigh-sensitive tin-oxide microsensors for H/sub 2/S detection

Ultrahigh-sensitivity SnO/sub 2/-CuO sensors were fabricated on Si(100) substrates for detection of low concentrations of hydrogen sulfide. The sensing material was spin coated over platinum electrodes with a thickness of 300 nm applying a sol-gel process. The SnO/sub 2/-based sensors doped with copper oxide were prepared by adding various amounts of Cu(NO/sub 3/)/sub 2/.3H/sub 2/O to a sol suspension. Conductivity measurements of the sensors annealed at different temperatures have been carried out in dry air and in the presence of 100 ppb to 10-ppm H/sub 2/S. The nanocrystalline SnO/sub 2/-CuO thin films showed excellent sensing characteristics upon exposure to low concentrations of H/sub 2/S below 1 ppm. The 5% CuO-doped sensor having an average grain size of 20 nm exhibits a high sensitivity of 2.15/spl times/10/sup 6/ (R/sub a//R/sub g/) for 10-ppm H/sub 2/S at a temperature of 85/spl deg/C. By raising the operating temperature to 170/spl deg/C, a high sensitivity of /spl sim/10/sup 5/ is measured and response and recovery times drop to less than 2 min and 15 s, respectively. Selectivity of the sensing material was studied toward various concentrations of CO, CH/sub 4/, H/sub 2/, and ethanol. SEM, XRD, and TEM analyses were used to investigate surface morphology and crystallinity of SnO/sub 2/ films.

Stress-assisted nickel-induced crystallization of silicon on glass

The effect of external mechanical stress on the crystallization of amorphous silicon deposited on thin, flexible glass substrates has been studied. A thin, 5–10 A, layer of nickel deposited on the surface of the amorphous silicon layer acted as the seed of crystallization and the crystallization was observed to initiate at the top surface and proceed down towards the glass substrate. Application of a tensile stress during the annealing stage led to a uniform, partial crystallization of the amorphous silicon for annealing temperatures as low as 310 °C. In contrast, the application of compressive stress led to buckling of the silicon films during annealing under mechanical stress and crystallization was nonuniform over the surface of the sample. The crystalline quality of the films was investigated using scanning electron microscopy, x-ray diffraction, and transmission electron microscopy analyses. In addition, lateral polycrystalline growth of the silicon was observed for the case in which the nickel seed ...

Thin-film tunneling transistors on flexible plastic substrates based on stress-assisted lateral growth of polycrystalline germanium

Stress-assisted Cu-induced lateral growth of polycrystalline germanium (poly-Ge) at temperatures as low as 150 °C has been exploited to fabricate thin-film tunneling transistors on flexible plastic substrates. Applying external compressive stress during annealing, leads to the lateral growth of poly-Ge from Cu-seeded drain/source regions, progressing into the channel area. A potential barrier is formed midway in the channel where the two lateral growth frontiers, emanating from source and drain seeded areas, meet each other. As confirmed by electrical measurements, the barrier is controlled by the gate bias. An ON/OFF ratio of 104 has been measured for these transistors, which shows the potential of these devices for switching applications.

Low temperature crystallization of germanium on plastic by externally applied compressive stress

The conventional Cu-induced crystallization of a-Ge has been facilitated by different types of external stress mechanically applied to the flexible substrate. It has been observed that in the case of compressive stress, crystallization becomes possible at temperatures as low as 130 °C and evolves as stress becomes more stringent. High electrical conductance and a hole mobility of 110 cm2/V s show the crystallinity of the Ge film, further confirmed by x-ray diffraction, scanning electron microscopy, and transmission electron microscopy analyses. The temperature of the annealing process (between 130 and 180 °C) expedites the process (from 6 to 1 h) as it is increased, but the principal mechanism seems to be independent of temperature. Temperatures higher than 180 °C are detrimental to the plastic substrate, polyethylene terephthalate. Evolution of cracks in Ge layer has been studied as the main consequence of the interfacial stress between Ge layer and substrate. The crack density was minimized by patternin...

Monolithic 3-D Integration of SRAM and Image Sensor Using Two Layers of Single-Grain Silicon

In this paper, we report monolithic integration of two single-grain silicon layers for static random access memory (SRAM) and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25-μm pixel size prepared on top of a three-transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.