M. Foresta

Electrical Characterization of Silicon Photo-Multiplier Detectors for Optimal Front-End Design

Silicon Photo-Multiplier (SiPM) detectors represent an attractive solution for the detection of low energy photons in several fields of both high energy physics and medical imaging. We present here an accurate electrical model for this kind of detectors, which can be conveniently used to perform reliable simulations at circuit level. A suitable extraction procedure for the parameters involved in the model is also described, based on both static and dynamic measurements. The proposed model allows to reproduce accurately the waveform of the signal generated by the SiPM when coupled to the front-end electronics, as shown by excellent fittings obtained between simulations and measurements taken on real devices. This is particularly useful in order to choose the most suitable front-end architecture for SiPM detectors, since the performance of the whole detection system, especially in terms of dynamic range and timing resolution, can be correctly predicted as a function of the detector parameters and of the main characteristics of the coupled electronics.

BASIC: An 8-channel front-end ASIC for Silicon Photomultiplier detectors

Multi-channel, integrated front-end electronics suitable for Silicon Photomultiplier detectors and mainly intended for medical imaging applications has been developed in a CMOS standard technology, according to a current-mode approach. Full exploitation of the good performance of the detector in terms of fast response and gain has been made possible by this design approach. An 8-channel, self-triggered prototype with an on-chip ADC has been designed and realized, also featuring a good degree of programmability and sparse read-out capabilities. Characterization measurements, carried out by coupling the circuit to both an injection capacitance and a SiPM manufactured from FBK-irst, confirm the expected results in terms of overall charge to voltage gain, dynamic range (more than 70pC at 1% non-linearity error), equivalent input noise charge (about 50fC) and timing accuracy.

ASIC development for SiPM readout

The design of CMOS front-end electronics suitable for Silicon Photo-Multipliers (SiPM) is described in this paper, starting with the specification of an accurate electrical model of the detector and its experimental validation. A novel current-mode solution is proposed for the preamplifier and the discriminator, to cope with the large dynamic range and the extremely fast rise time of the detector signal. Experimental results achieved from front-end prototypes designed according to this current-mode approach demonstrate its effectiveness: dynamic range of the order of 50 pC and timing accuracy of the electronics alone of about 30 ps have been measured.

Preliminary results from a current mode CMOS front-end circuit for silicon photomultiplier detectors

We propose a CMOS front-end circuit suitable for Silicon Photomultiplier detectors (SiPM) based on a current buffer, as input stage, which features small input impedance and large bandwidth, thanks to the application of current feedback techniques. The current mode approach enhances the dynamic range of the front-end and does not suffer from possible voltage limitations due to deep-submicron CMOS implementation. We report the first measurement results obtained by coupling the circuit prototype to a SiPM detector excited by a blue LED light source. The measurements confirm the effectiveness of the proposed front-end approach and demonstrate its capability of managing large current signals with good linearity.

Current-mode front-end electronics for silicon photo-multiplier detectors

Silicon photo-multiplier (SiPM) detectors represent an attractive solution for the detection of low energy photons in several fields of both high energy physics and medical imaging. Here we review a recently proposed electrical model for this kind of detectors, which can be conveniently used to perform reliable simulations at circuit level and allows to reproduce accurately the waveform of the signal generated by the SiPM when coupled to the front-end electronics. This is particularly useful in order to choose the most suitable front-end architecture for SiPM detectors. In particular, we propose a front-end architecture based on a current buffer as input stage, featuring small input impedance and large bandwidth due to the use of a current feedback. Moreover the current-mode approach enhances the dynamic range as it does not suffer from possible voltage limitations due to deep-submicron implementations. Two alternative circuit solutions have been designed and manufactured in a 0.35 mum CMOS process. We report the first measurement results obtained by coupling the two prototypes to a SiPM detector excited by a pulsed infrared laser. The measurements allow to validate the functionality of the proposed front-end architecture and demonstrate its capability of managing large current signals with good linearity.

A novel output baseline holder circuit for CMOS front-end analog channels

We propose a novel CMOS baseline holder circuit, able to keep at a specified value the dc output voltage of typical integrated front-end analog channels coupled to silicon detectors, for both high energy physics and medical imaging applications. The circuit, together with the shaping filter, forms a slow feedback loop. A very low frequency pole is obtained in the feedback path, without using large capacitance values, by exploiting a circuit technique based on the properties of operational transconductance amplifiers. The huge time constant achievable with the proposed technique makes this solution suitable to be applied to high-gain front-end circuits, since the stability conditions can be easily fulfilled. Two different non-linearity effects are exploited to limit the baseline shift which occurs at high signal rates. The circuit has been designed in a standard CMOS 0.35μm technology and the first experimental results obtained from different prototypes show the effectiveness of the proposed solution.

Front-end electronics for Silicon photo-multipliers coupled to fast scintillators

As a result of a comprehensive study aimed at the development of integrated front-end electronics suitable for Silicon Photomultiplier detectors, a 32-channel self-triggered ASIC has been designed in a standard 0.35μm CMOS technology. Characterization measurements, carried out exploiting an external injection capacitance, demonstrate that the architecture of the analog channel, based on a full current-mode approach, allows to achieve very good performance in terms of dynamic range (around 70pC), bandwidth and timing accuracy (σ@118ps). The ASIC has been used in self-triggered mode to read-out a SiPM from Hamamatsu, coupled to a small LYSO scintillator, and the resulting spectra obtained by exposing the detector to different radiation sources confirm the effectiveness of our design approach. Eventually, some modifications to the architecture of the ASIC are proposed to improve its performance in the detection of low light levels and to enhance the effectiveness of the sparse read-out acquisition mode. These new features have been implemented in a further version of the ASIC, containing also an 8-bit, 20Ms/s embedded ADC designed on purpose, which has been already submitted for fabrication.

Experimental results from an analog front-end channel for silicon photomultiplier detectors

Silicon photomultipliers (SiPM) have rapidly increased their popularity among scientists and engineers involved in the detection of low energy photons over a wide range of applications, thanks to their characteristics which compare favourably with those of photomultiplier tubes (PMT), in terms of bias voltage, immunity to magnetic fields and size.

A novel baseline holder circuit for nuclear imaging front-end electronics

A novel baseline holder circuit (BLH) is proposed here, able to produce a stable baseline level at the output of a typical analog front-end channel for particle detectors, both at dc and at high rate operation. The circuit is suitable to be used in modern high-sensitivity gamma-ray medical imaging systems, where high gain shapers are required. A very low frequency pole, which is fundamental for the stability of the shaper-BLH loop, is realized by means of operational transconductance amplifiers (OTA), which allow to save area, making the circuit suitable for the integration in a standard CMOS technology. Non-linearity effects have been exploited to reduce the baseline shift at high input signal rates, due to the low dc gain of the shaper+BLH system. The circuit has been designed in a standard 0.35 mum CMOS technology, and extensive simulations prove the effectiveness of the adopted solutions. A baseline drift of less than 1.8 mV has been observed for a 30 KHz input rate.

A 4D-PET block detector based on Silicon Photomultipliers

Next generation PET scanners should fulfill very high requirements in terms of spatial, energy and timing resolution. Modern scanner performances are inherently limited by the use of standard photomultiplier tubes. The use of Silicon Photomultiplier (SiPM) matrices is proposed for the construction of a 4D PET module based on LYSO continuos crystals, which is envisaged to replace the standard PET block detector. The module will provide a submillimetric spatial resolution on the photon hit position, performing at the same time, the Depth Of Interaction (DOI) calculation and the Time Of Flight (TOF) measurement. The use of large area multi-pixel Silicon Photomultiplier (SiPM) detectors requires the development of a multichannel Digital Acquisition system (DAQ) as well as of a dedicated front-end in order not to degrade the intrinsic detector capabilities. At the University of Pisa and INFN Pisa we have developed a flexible and modular DAQ system for the read-out of 2 module in time coincidence for Positron Emission Tomography (PET) applications. Here we describe the acquisition system architecture and its characterization measurements.