M. Guillorn

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

We demonstrate the worlds first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs

This work demonstrates, for the first time, the reduction of random telegraph noise (RTN) in high-к / metal gate (HK / MG) stacks incorporated in 22 nm generation FETs. Many thousands of such FETs have been fabricated, measured, and analyzed using a statistical technique to separate RTN as a major noise component from 1/f noise as a minor component. Based on a statistical comparison of these FETs, we find that high temperature forming gas annealing can suppress RTN threshold voltage variation (ΔVth). In addition, properly annealed HK FETs have smaller RTN ΔVth than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK / MG. Based on these results, we project that random dopant fluctuations will have a greater impact on SRAM yield than RTN until at least the 15 nm generation, for doped channel FETs.

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

We demonstrate a process flow for creating gate-all-around (GAA) Si nanowire (SiNW) MOSFETs with minimal deviation from conventional replacement metal gate (RMG) finFET technology as used in high-volume manufacturing. Using this technique, we demonstrate the highest DC performance shown for GAA SiNW MOSFETs at sub-100 nm gate pitch, and functional high-speed ring oscillators.

Computational Aspects of Optical Lithography Extension by Directed Self-Assembly

EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.

Gate-all-around silicon nanowire MOSFETs and circuits

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.

Computational lithography platform for 193i-guided directed self-assembly

We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s publication [1]. Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before [2], we implement a 2D phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more predictive than compact model but much faster then the physics-based MC model. However simplifying the model might lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm based lithography process using DSA.

Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?

Abstract. We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.