M. Haney

The FASTBUS Segment Interconnect

The FASTBUS Segment Interconnect provides a communication path between two otherwise independent, asynchronous bus segments. In particular, the segment interconnect links a backplace (crate) segment to a cable segment. All standard FASTBUS address and data transactions can be passed through the SI, or any number of SIs and segments in a path. Thus systems of arbitrary connection complexity can be formed, allowing simultaneous independent processing, yet still permitting devices associated with one segment to be accessed from others. The model S1 segment interconnect being built at the University of Illinois supports these and other important features.

RTES demo system2004

The RTES Demo System 2004 is a prototype for reliable, fault-adaptive infrastructure applicable to commodity-based dedicated application computer farms, such as the Level 2/3 trigger for the proposed BTeV high energy physics project. This paper describes the prototype, and its demonstration at the 11th IEEE Real Time and Embedded Technology Applications Symposium, RTAS 2005.

The CLEO-III trigger: axial and stereo tracking

The tracking subsystem of the CLEO-III Trigger consists of separate axial and stereo tracking pattern-matching modules, whose products are time-aligned and spatially correlated to provide pipelined trigger information every 42 ns with a latency of approximately 2 /spl mu/s. This paper describes the pipelined signal processing and pattern recognition schemes used by the axial and stereo electronics to provide the information necessary to make trigger decisions. Extensive use of in-system field programmable gate arrays support path finding and timing information extraction.

Progress in absorber R & D for muon cooling

A stored-muon-beam neutrino factory may require transverse ionization cooling of the muon beam. We describe recent progress in research and development on energy absorbers for muon-beam cooling carried out by a collaboration of university and laboratory groups.

The CLEO-III trigger: level 1 decision and gating

The Level 1 Decision and Data Flow/Control subsystems of the CLEO-III Trigger produce and distribute a trigger decision every 42 ns based on input from calorimetry and tracking subsystems. This paper describes the free-running pipelined trigger decision logic that correlates axial and stereo tracking information, and combines time-aligned calorimetry information onto a common backplane. Programmable trigger decision boards monitor this backplane, and can be configured as desired to respond to a wide variety of trigger conditions. The resulting trigger decision is regulated by a throttling mechanism that allows the data acquisition system to modulate the trigger rate to maximize throughput without buffer overrun. A central signal distribution mechanism delivers the trigger decision and system clock to the front-end electronics.

The CLEO-III trigger: Decision and gating

The CLEO-III Trigger provides a trigger decision every 42 ns, with a latency of approximately 2.5 /spl mu/s. This paper describes the free-running, pipelined trigger decision logic, the throttling mechanism whereby the data acquisition system can modulate the trigger rate to maximize throughput without buffer overrun, and the subsequent signal distribution mechanism for delivering the trigger decision to the front-end electronics. This paper also describes the multilevel simulation methods employed to allow detailed low-level models of trigger components to be co-simulated with more abstract system models, thus allowing full system modeling without incurring prohibitive computational overheads.

The DECam Data Acquisition and Control System

In this paper we describe the data acquisition and control system of the Dark Energy Camera (DECam), which will be the primary instrument used in the Dark Energy Survey (DES). DES is a high precision multibandpath wide area survey of 5000 square degrees of the southern sky. DECam currently under construction at Fermilab will be a 3 square degree mosaic camera mounted at the prime focus of the Blanco 4m telescope at the Cerro-Tololo International Observatory (CTIO). The DECam data acquisition system (SISPI) is implemented as a distributed multi-processor system with a software architecture built on the Client-Server and Publish-Subscribe design patterns. The underlying message passing protocol is based on PYRO, a powerful distributed object technology system written entirely in Python. A distributed shared variable system was added to support exchange of telemetry data and other information between different components of the system. In this paper we discuss the SISPI infrastructure software, the image pipeline, the observer interface and quality monitoring system, and the instrument control system.

Progress in absorber R&D 2: windows

A program is under way to develop liquid-hydrogen energy absorbers for ionization cooling of muon-beam transverse emittance. Minimization of multiple-scattering-induced beam heating requires thin windows. The first window prototype has been destructively tested, validating the finite-element-analysis model and the design approach.

The CLEO-III trigger: analog and digital calorimetry

The calorimetry subsystem of the CLEO-III Trigger incorporates both analog and digital electronics to provide pipelined trigger information every 42 ns with a latency of approximately 2.5 /spl mu/s. This paper describes the pipelined signal-processing and pattern-recognition schemes used to provide calorimeter information to the experiment trigger with somewhat greater emphasis on the analog components of the system. Analog processing is employed to address the quantization error caused by split energy deposition in adjacent calorimeter cells, and digital field programmable gate arrays are used extensively to filter and categorize the calorimeter energy topology. Timing, geographical, and energy information are all available for use in the calorimeter trigger.

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.