M. Inaba

PHENIX central arm particle ID detectors

Abstract The Ring-Imaging Cherenkov (RICH) and the Time-of-Flight (ToF) systems provide identification of charged particles for the PHENIX central arm. The RICH is located between the inner and outer tracking units and is one of the primary devices for identifying electrons among the very large number of charged pions. The ToF is used to identify hadrons and is located between the most outer pad chamber (PC3) and the electromagnetic calorimeter. A Time Zero (T0) counter that enhances charged particle measurements in p–p collisions is described. Details of the construction and performance of both the RICH, ToF and T0 are given along with typical results from the first PHENIX data taking run.

Realization of NMAX and NMIN functions with multi-valued voltage comparators

In this paper, realization of three fundamental functions, NOT, negated MAX and negated MIN functions, in the voltage-mode quaternary logic is presented. First, the high-performance NOT circuits with the down literal circuits are composed. The proposed NOT circuits have the quantified effect to realize high noise margins in the voltage-mode quaternary logic circuits. Next, we propose the voltage comparator with the NOT circuit, and, as applications of the voltage comparator, NMAX and NMIN circuits are designed. They can realize the negated MAX and the negated MIN functions, respectively. The advantages of these proposed circuits are fabrication with a conventional CMOS process, high noise margins of more than 0.46[V] and low power consumption with peak of less than 350[/spl mu/W] under 3.0[V] of the supply voltage in verification using HSPICE simulations.

Multi-valued flip-flop with neuron-CMOS NMIN circuits

In this paper, the implementation and verification of the fundamental flip-flops for the voltage-mode multi-valued logic circuits on a conventional CMOS VLSI chip are presented. Using the quantized NMIN circuits and the analog NMIN circuits, two types of the multi-valued R-S flip-flop are designed like a wide-use R-S flip-flop with NAND circuits and are applied to the D flip-flop for multi-valued memory. In verification through HSPICE simulation, the proposed flip-flops perform with good results such as high noise margins and low power consumption.

Multi-valued logic pass gate network using neuron-MOS transistors

A multi-valued logic (MVL) pass gate is an important element to configure multi-valued logic networks. Different from binary pass gates, multiple logical levels are required to be discriminated in MVL pass gates. In this paper, according to the feature of the threshold operation of a neuron MOS transistor (VMOS), two types of MVL pass gates using /spl nu/MOS are presented. One type, a CMOS MVL pass gate with VMOS down literal circuit, is composed of a CMOS pass gate and a VMOS threshold gate (/spl nu/MOS down literal circuit (DLC)). The discrimination between different MVL signals is realized by the threshold gate. Another type, a /spl nu/MOS hybrid pass gate, consists of a /spl nu/MOS transistor, a MOS transistor and a binary inverter. The VMOS transistor as used as a pass transistor, and the threshold discrimination is directly implemented by the VMOS pass gate. The latter is more compact than the former. The number of transistors and the layout area of the MVL network can be reduced by using /spl nu/MOS hybrid pass gates, while the bias setting is easier by using CMOS MVL pass gates. The common advantages of the proposed pass gates are low fabrication cost and possibility to build reconfigurable networks.

Design of a floating node voltage-controlled linear variable resistor circuit

The floating node voltage-controlled linear variable resistor circuit is a versatile building block in several analog signal processes such as telecommunications and electronics. Floating node voltage-controlled linear variable resistor circuits have been developed by using MOSFET components. In this paper, a floating node voltage-controlled linear variable resistor circuit is proposed. The advantage of the proposed circuit is that it is both linear and compact. The utility of the proposed circuit was confirmed by PSpice simulations. A tunable cut off frequency of an RC filter has been applied with the proposed circuit as an analog building block and the results are presented here. This proposed floating node voltage-controlled linear variable resistor circuit has high linearity and a wide controlling voltage that does not depend on the supply voltage. Evaluation of the floating node variable resistor showed that when the supply voltage was 5 volts, and the bias voltage was from 0 to 1.5 volts, the value stayed in a variable range of from 58 k/spl Omega/ to 1600 k/spl Omega/ and the power consumption was 132.5 /spl mu/W, and -3 dB bandwidth 25 kHz. The simulation results are reported in this paper.

Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process

In this paper, the transistor-level layouts and the experiment results of the down literal circuit (DLC) and the analog inverter (AINV) on a CMOS double- poly silicon process are presented. DLC and AINV are the voltage-mode circuits to realize the down literal function with a variable threshold and the inverse function, respectively. Through the experiment of test- production LSI chips, the good transfer characteristics of DLC and AINV are confirmed. For instance, the threshold voltage of DLC is in error by less than 0.03[V] only. AINV achieves the high linearity within 86% of all signal range and the errors of the output voltage are within +0.01 [V] and -0.11 [V]. The results fully satisfy the requirements for the 5-volt 6-value logic circuits or more. And, the voltage comparator is taken up as an application of DLC and AINV.

A reaction plane detector for PHENIX at RHIC

Abstract A plastic scintillator paddle detector with embedded fiber light guides and photomultiplier tube readout, referred to as the Reaction Plane Detector (RXNP), was designed and installed in the PHENIX experiment prior to the 2007 run of the Relativistic Heavy Ion Collider (RHIC). The RXNPs design is optimized to accurately measure the reaction plane (RP) angle of heavy-ion collisions, where, for mid-central s NN = 200 GeV Au+Au collisions, it achieved a 2nd harmonic RP resolution of ∼ 0.75 , which is a factor of ∼ 2 greater than PHENIXs previous capabilities. This improvement was accomplished by locating the RXNP in the central region of the PHENIX experiment, where, due to its large coverage in pseudorapidity ( 1.0 | η | 2.8 ) and ϕ ( 2 π ), it is exposed to the high particle multiplicities needed for an accurate RP measurement. To enhance the observed signal, a 2-cm Pb converter is located between the nominal collision region and the scintillator paddles, allowing neutral particles produced in the heavy-ion collisions to contribute to the signal through conversion electrons. This paper discusses the design, operation and performance of the RXNP during the 2007 RHIC run.

Linear and Compact Floating Node Voltage-Controlled Variable Resistor Circuit

In this letter, my proposals for a Floating node voltage-controlled Variable Resistor circuit (FVR) are based upon its advantages as linear and compact. The performance of the proposed circuit was confirmed by PSpice simulation. The simulation results are reported in this letter.

PHENIX Fast TOF

This is a technical scope of work (TSW) between the Fermi National Accelerator Laboratory (Fermilab) and the experimenters of PHENIX Fast TOF group who have committed to participate in beam tests to be carried out during the FY2014 Fermilab Test Beam Facility program. The goals for this test beam experiment are to verify the timing performance of the two types of time-of-flight detector prototypes.

Optimization of Current-Mode MVD-ORNS Arithmetic Circuits

In this paper, optimization and verification of the current-mode fundamental arithmetic circuits employing MVD-ORNS are presented. MVD-ORNS is the redundant number system using logic levels in the multiple-valued logic. In order to get over weak points of ordinary circuits, the algorithms and circuit components for addition, subtraction and multiplication are reconsidered through the logical analysis and HSPICE simulation with CMOS 0.35 micrometer device parameters. As results in the 4-bit multiplier, the maximum logic level and the number of modulo operations in the series connection are successfully reduced to 29 from 49 and to 2 from 3, respectively. HSPICE simulation also shows the good results, for example the proposed switched current mirrors are very effective to bring both of the stable operation and low power dissipation to the current-mode arithmetic circuits. The proposed MVD-ORNS circuits are expected to realize the high-speed full-parallel calculation without any carry/borrow propagation.