M.J. Deen

An effective gate resistance model for CMOS RF and noise modeling

A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices. The accuracy of the model is validated with 2D simulations and experimental data. In addition, the effect of the gate resistance on the device noise behavior has been studied with measured data. The result shows that an accurate gate resistance model is essential for the noise modeling.

A wireless wearable ECG sensor for long-term applications

Ubiquitous vital signs sensing using wireless medical sensors are promising alternatives to conventional, in-hospital healthcare systems. In this work, a wearable ECG sensor is proposed. This sensor system combined an appropriate wireless protocol for data communication with capacitive ECG signal sensing and processing. The ANT protocol was used as a low-data-rate wireless module to reduce the power consumption and size of the sensor. Furthermore, capacitive ECG sensing is a simple technique that avoids direct contact with the skin and provides maximum convenience to the user. In our work, small capacitive electrodes were integrated into a cotton T-shirt together with a signal processing and transmitting board on a two-layer standard printed circuit board design technology. The entire system has small size, is thin, and has low power consumption compared to recent ECG monitoring systems. In addition, appropriate signal conditioning and processing were implemented to remove motion artifacts. The acquired ECG signals are comparable to ones obtained using conventional glued-on electrodes, and are easily read and interpreted by a cardiologist.

A low-noise, low-power VCO with automatic amplitude control for wireless applications

Voltage controlled oscillators (VCOs) used in portable wireless communications applications, such as cellular telephony, are required to achieve low phase-noise levels while consuming minimal power. This paper presents the design challenges of a VCO with automatic amplitude control, which operates in the 300 MHz to 1.2 GHz frequency range using different external resonators. The VCO phase noise level is -106 dBc/Hz at 100-KHz offset from an 800-MHz carrier, and it consumes 1.6 mA from a 2.7-V power supply. An extensive phase-noise analysis is employed for this VCO design in order to identify the most important noise sources in the circuit and to find the optimum tradeoff between noise performance and power consumption.

Model for the field effect from layers of biological macromolecules on the gates of metal-oxide-semiconductor transistors

The potential diagram for field-effect transistors used to detect charged biological macromolecules in an electrolyte is presented for the case where an insulating cover layer is used over a conventional eletrolyte-insulator metal-oxide-semiconductor (EIMOS) structure to tether or bind the biological molecules to a floating gate. The layer of macromolecules is modeled using the Poisson-Boltzmann equation for an ion-permeable membrane. Expressions are derived for the charges and potentials in the EIMOS and electrolyte-insulator-semiconductor structures, including the membrane and electrolyte. Exact solutions for the potentials and charges are calculated using numerical algorithms. Simple expressions for the response are presented for low solution potentials when the Donnan potential is approached in the bulk of the membrane. The implications of the model for the small-signal equivalent circuit and the noise analysis of these structures are discussed.

Organic Thin-Film Transistors: Part I—Compact DC Modeling

A generic analytical model for the current-voltage characteristics of organic thin-film transistors (OTFTs) is derived. Based on this generic model, a TFT compact dc model that meets the requirements for compact modeling, including for computer circuit simulators, is proposed. The models are fully symmetrical, and the TFT compact dc model covers all regimes of TFT operation-linear and saturation above threshold, subthreshold, and reverse biasing. The empirical fitting parameters are mostly eliminated from the characteristic equations. The developed models are also in close correspondence to several physical, parametric, and limiting models for current-voltage and mobility characteristics. An essential practical feature of the TFT compact dc model is that the model is both upgradable and reducible, allowing for easier implementation and modifications and also simultaneously allowing for separation of characterization techniques. This allows for systematic fitting of experimental data with large scattering in the values, but at the same time, preserving consistently the OTFT behavior in the model.

Fully Integrated Single Photon Avalanche Diode Detector in Standard CMOS 0.18-

Avalanche photodiodes (APDs) operating in Geiger mode can detect weak optical signals at high speed. The implementation of APD systems in a CMOS technology makes it possible to integrate the photodetector and its peripheral circuits on the same chip. In this paper, we have fabricated APDs of different sizes and their driving circuits in a commercial 0.18-mum CMOS technology. The APDs are theoretically analyzed, measured, and the results are interpreted. Excellent breakdown performance is measured for the 10 and 20 m APDs at 10.2 V. The APD system is compared to the previous implementations in standard CMOS. Our APD has a 5.5% peak probability of detection of a photon at an excess bias of 2 V, and a 30 ns dead time, which is better than the previously reported results.

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This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 /spl mu/m CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.

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Compact modeling of the most important high-frequency (HF) noise sources of the MOSFET is presented in this paper, along with challenges in noise measurement and deembedding of future CMOS technologies. Several channel thermal noise models are reviewed and their ability to predict the channel noise of extremely small devices is discussed. The impact of technology scaling on noise performance of MOSFETs is also investigated by means of analytical expressions. It is shown that the gate tunneling current has a significant impact on MOSFETs noise parameters, especially at lower frequencies. Limitations of some commonly used noise models in predicting the HF noise parameters of modern MOSFETs are addressed and methods to alleviate some of the limitations are discussed

Channel noise modeling of deep submicron MOSFETs

An extraction method to obtain the induced gate noise (i~/sub g/~/sup 2/~) channel noise (i~/sub d/~/sup 2/~), and their cross correlation (i~/sub g/~i~/sub d/~*~) in submicron MOSFETs directly from scattering and RF noise measurements has been presented and verified by measurements. In addition, the extracted induced gate noise, channel noise, and their correlation in MOSFETs fabricated in 0.18-/spl mu/m CMOS process versus frequencies, bias conditions, and channel lengths are presented and discussed.

High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues

Abstract In this paper, a model is proposed which can predict accurately both ac and noise performance (all four noise parameters: minimum noise figure NF min , equivalent noise resistance R n , optimized source resistance R opt and reactance X opt ) of MOSFETs based on s -parameter and noise measurements at microwave frequencies. This model includes the relevant high frequency noise sources (i.e. the channel thermal noise, the induced gate noise and its correlation with the channel thermal noise and the thermal noise from the gate and parasitic resistances). In order to confirm the accuracy of the model and obtain the intrinsic scattering and noise parameters of devices, two de-embedding techniques (probe pad equivalent circuit modeling and direct parasitic noise de-embedding) have been used to de-embed the probe pad parasitics from the measured noise and s -parameters of the device-under-test (DUT). In addition, because of the complexity of this noise model, a direct calculation technique for calculating the four noise parameters was developed based on the small-signal transistors model. Finally, the impact of gate resistance, and the noise improvement using multi-finger gate design are investigated.