M.K. Ibrahim

Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2/sup n/ arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A twos complement digit-serial architecture which can operate on both negative and positive numbers is also presented.

Novel RNS structures for the moduli set (2 n −1, 2 n , 2 n +1)

Abstract In this paper, new architectures for fast and efficient conversions from the weighted binary numbers to their 3-moduli (2 n − 1, 2 n , 2 n + 1) residue number representation and vice versa is described. The converters are realised using carry save arithmetic and a novel modulo adder. The new adder is based on generating the carry-out bit first and feeding it forward as carry-in to perform modulo reduction. Since the choice of the adder is critical, the CLA adder which has the best performance when compared with other adders is used. An RNS multiplier for the same moduli set using the carry save scheme and the modulo adder is also described. Also, in this paper an RNS FIR filter based on the carry save arithmetic and the new modulo multiplier is presented. Comparison with existing designs has shown that the new designs based on the new modulo adder and the carry save arithmetic are much faster and have much less hardware than the existing structures.

A new digit-serial divider architecture

A new simple algorithm for performing digit-serial division is described. The non-restoring binary division algorithm has been modified to obtain an equivalent algorithm suitable for general radix. Also, a digit-serial pipelined divider architecture is presented to carry out division digit serially so that many samples can be processed simultaneously. Our architecture is different from existing digit-serial dividers in that it is based on a radix-2 n division algorithm. It is simple and general for any value of n or any number of digits. Furthermore, it can be made fully pipelined and can deal with positive as well as negative operands.

Bit-level pipelined digit-serial multiplier

A new cell architecture for high performance digit-serial computation is presented. The design of this cell is based on the feed forward of the carry digit, which allows a high level of pipelining to increase the throughput rate with minimum latency. This will give designers greater flexibility in finding the best trade-off between hardware cost and throughput rate. A twin-pipe architecture to double the throughput rate of digit-serial/parallel multipliers is also presented. The effects of the number of pipelining levels and the twin architecture on the throughput rate and hardware cost are presented. A twos complement digit-serial/parallel multiplier which can operate on both negative and positive numbers is also presented.

Dual basis digit serial GF(2 m ) multiplier

A new digit serial GF(2 m ) multiplier based on the dual basis representation is presented for the first time in this paper. The multiplier is suitable for large word lengths such as those found in cryptosystems. Digit serial computations give a much better trade-off between area and speed in comparison with bit-parallel realization, which is too costly, and bit-serial realization which is too slow. The new multiplier is based on a look-ahead technique which serves to overcome the recursive algorithm used to calculate the extra elements of the operand represented in the dual basis prior to the multiplication process. This recursive algorithm is the main bottleneck for digit-serial multiplication. Unlike existing design, the new multiplier has low latency, and its digit size is not restricted by the type of primitive polynomial being used. A systolic version of the new multiplier, suitable for VLSI implementation, is also presented.

A new high radix non-restoring divider architecture

Abstract This paper presents a new radix-2k non-restoring area-efficient fast divider architecture where k quotient bits (one digit) are calculated in one step. Unlike the existing non-redundant high radix architecture, the proposed architecture makes use only of the odd multiple values of the divisor. Therefore, it requires nearly half the area of the existing one. The input operands are in the twos complement form, whereas the output quotient is in theirs complement form. This architecture is general for any value of k and can deal with positive and negative operands. Any adder can be used in the basic cell. This can be a ripple carry adder or a carry lookahead adder.

Radix multiplication algorithms

Abstract Several novel radix iterative multiplication algorithms are presented. They can be used to design iterative array multipliers, serial/parallel multipliers and serial multipliers. Due to the iterative nature of the algorithms, the resulting structures are regular, modular and require localized communication only, which makes them suitable for VLSI implementation. The advantage of the structures based on the radix approach is that the architecture of the basic cell is not fixed for all radices. Any architecture can be used so long as its functionality satisfies the corresponding radix multiplication algorithm. The new algorithms can be used as a structured multiplier-design methodology that will allow designers to find the best compromise between hardware cost and multiplication time. In this approach, the multiplier architecture is first defined in terms of the radix-2nmultiplication algorithm which is general for all n. This results in an architecture being available for every n. The trade-off be...

Design of a square-root architecture: digit-serial approach

Abstract A new digit-serial square-root architecture based on radix-2n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtract (CAS) cells. We present two CAS cell architectures. The first is based on the conventional carry feed-back digit serial adder. The second is based on the carry feed-forward adder structure which results in the first reported square-root architecture that can be pipelined down to the bit-level. Furthermore, there is no specification of the type of adder used in the CAS cell. It can be a carry look-ahead or a carry propagate adder. The proposed architecture is general for any digit size and any wordlength.