M.M. Samsom

Design And Implementation Of A Linear-phase Equalizer In Digital Audio Signal Processing

This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the signal processing algorithms constituting the global design of the equalizer are computer simulated. The third step includes the realization of the equalizer design using one or more programmable DSP?s. In order to minimize the number of DSP chips necessary for the realization, this step requires the optimization of the structure and mapping of the algorithm on the resources of the DSP. The number of processor cycles is crucial in this optimization. The purpose of the resulting prototype is to test and to validate in a digital audio environment the specification generated in the first step. The programmability of the DSP?s allows for specification changes at this stage of the project. The fourth step is the VLSI implementatin of the validated algorithm of the previous phase. For this purpose the structure of the algorithm is optimized in order to take full advantage of the silicon resources. Speed and required area are the crucial parameters in this optimization. The final step includes the testing of the completed chips together with a parallel designed and realized PCB in a digital audio environment. The presentation will emphasize the algorithmic and design considerations together with the results.

A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme

Some image processing applications (e.g. computer graphics and robot vision) require the rotation, scaling and translation of digitized images in real-time (25–30 images per second). Todays standard image processors can not meet this timing constraint so other solutions have to be considered. This paper describes a multi-ASIC solution which is capable of doing the image processing tasks in real-time. The first ASIC is a so-called affine transformer which calculates a one-dimensional coordinate every 25 ns. The second ASIC is a bilinear interpolator which calculates an interpolated value from four known surrounding values, again every 25 ns. This ASIC is designed in a modular setup which results in a flexible accuracy of the interpolation. If more accurate interpolation is required, another ASIC (containing an interpolation stage) is used. In this way for each application a proper accuracy is implemented, reaching optimal silicon area utilization and desired accuracy of interpolation. Using two affine transformers (for obtaining a two dimensional coordinate pair) and an interpolator, one can build a system which can translate, rotate and scale an image of size 1024 * 1024 in real-time (25–30 images per second). In this paper the system as well as the design of the ASICs are presented.