M. Menouni

Digital architecture and interface of the new ATLAS Pixel Front-End IC for upgraded LHC luminosity

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.

1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades

The radiation tolerance of 65 nm bulk CMOS devices was investigated using 10 keV X-rays up to a Total Ionizing Dose (TID) of 1 Grad. Irradiation tests were performed at room temperature (25°C) as well as at low temperature (−15°C). The implications on the DC performance of n and p channel transistors are presented. For small size devices, a strong performance degradation is observed from a dose of 100 Mrad. Irradiations made at room temperature up to 1 Grad show a complete drive loss in PMOS devices, due to decreasing transconductance. When the irradiation is conducted at −15°C, the devices show less radiation damage. Annealing helps recovering a small part of the drive capabilities of the small size devices, but the threshold voltage shift is still high and might compromise the operation in some digital applications.

The Level-0 muon trigger for the LHCb experiment

A very compact architecture has been developed for the first level Muon Trigger of the LHCb experiment that processes 40 millions of proton-proton collisions per second. For each collision, it receives 3.2 kBytes of data and it finds straight tracks within a 1.2 microseconds latency. The trigger implementation is massively parallel, pipelined and fully synchronous with the LHC clock. It relies on 248 high density Field Programable Gate arrays and on the massive use of multigigabit serial link transceivers embedded inside FPGAs.

Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

A new pixel Front-End Integrated Circuit is being developed in a 130nm technology for use in the foreseen b-layer upgrade of the ATLAS Pixel Detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the End-of-Column, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

PIXSIC: A Pixellated Beta-Microprobe for Kinetic Measurements of Radiotracers on Awake and Freely Moving Small Animals

We present a design study of PIXSIC, a new β+ radiosensitive microprobe implantable in rodent brain dedicated to in vivo and autonomous measurements of local time activity curves of beta radiotracers in a small (a few mm3) volume of brain tissue. This project follows the initial β microprobe previously developed at IMNC, which has been validated in several neurobiological experiments. This first prototype has been extensively used on anesthetized animals, but presents some critical limits for utilization on awake and freely moving animals. Consequently, we propose to develop a wireless setup that can be worn by an animal without constraints upon its movements. To that aim, we have chosen a Silicon-based detector, highly β sensitive, which allows for the development of a compact pixellated probe (typically 600 × 200 × 1000 μm3), read out with miniaturized wireless electronics. Using Monte-Carlo simulations, we show that high resistive Silicon pixels are appropriate for this purpose, assuming that the pixel dimensions are adapted to our specific signals. More precisely, a tradeoff has to be found between the sensitivity to β+ particles and to the 511 keV j background resulting from annihilations of β+ with electrons. We demonstrate that pixels with maximized surface and minimized thickness can lead to an optimization of their β+ sensitivity with a relative transparency to the annihilation background.

The design for test architecture in digital section of the ATLAS FE-I4 chip

This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used for the detector construction, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.

Simulation Results for PLATO: A Prototype Hybrid X-Ray Photon Counting Detector with a Low Energy Threshold for Fusion Plasma Diagnostics

PLATO is a prototype hybrid X-ray photon counting detector that has been designed to meet the specifications for plasma diagnostics for the WEST tokamak platform (Tungsten (W) Environment in Steady-state Tokamak) in southern France, with potential perspectives for ITER. The objective is to detect X-ray fluorescence photons emitted by a tokamak plasma at energies as low as 3 keV. Therefore, PLATO represents a customized solution that fulfills high sensitivity, low dispersion and high photon counting rate. The PLATO prototype matrix is composed of 16 x 16 pixels with a 70 μm pixel pitch. Each pixel contains a charge sensitive amplifier, two discriminators and two 12-bit counters/ shift registers. New techniques have been used in analog sensitive blocks to minimize noise coupling through supply rails and substrate, and to suppress threshold dispersion across the matrix. For an input capacitance of 250 fF and a maximum photon counting rate of 12 × 107 photons/s/mm2, simulation results indicate an input referred equivalent noise charge of 42 e-rms and a high response linearity for photon energies between 2 and 10 keV. A new feedback technique has been implemented that allows a very high conversion gain of 72 mV/ke- while maintaining low pixel to pixel dispersion. Moreover, the pixel has been optimized for low power consumption of 5.2 μW/pixel. The pixel can be programmed in a ‘two energy threshold’ mode with 2 x 12-bit counters, or ‘one energy threshold’ mode with a 24-bit counter. Furthermore, leakage current is compensated up to 10 nA/pixel. The Plato ASIC has been designed in TSMC CMOS 0.13 μm technology and is scheduled for a fabrication run in May 2016. The prototype chip should be tested electrically, as well as bump bonded to silicon detector

High speed parallel optical links for the LHCb muon trigger

Twelve deserializer chips recovering the original 32-bits data words from the high speed signals. The principles retained to transport binary data between the muon detector and the muon trigger for the LHCb experiment is based on the serialization of the binary detector data ; the use of optical links ; and the use of high integration optical devices. The optical modules are designed to operate on multimode fiber at a nominal wavelength of 850 nm.