M. Mony

Free-space optical link with spatial redundancy for misalignment tolerance

Free-space optical interconnects can provide high bandwidth with no physical contact, but suffer from poor tolerances to misalignment. In order to obtain high misalignment tolerances, we propose the use of an active alignment scheme in conjunction with an optimized optical design. The active alignment scheme uses a redundant set of optical links and the active selection of the best link. The optical design maximizes the alignment tolerances between the two boards to /spl plusmn/1 mm of lateral and /spl plusmn/1/spl deg/ of angular misalignment for a target data rate of 1.25 Gb/s.

Bulk electro-optic deflector-based switches

We propose two novel electro-optic (EO) deflectors based on two new nonrectangular geometries: the parabolic and the half-horn configurations. These devices not only provide excellent deflection angles, but also have the potential to build nonblocking 2 x 2 optical switches. A deflector figure of merit is defined, and comparisons with existing EO deflectors are given. Devices fabricated in LiTaO(3) demonstrate 3 dB of average insertion loss and 3 degrees deflection angles. These results represent the best deflection performances to our knowledge reported to date for bulk EO deflectors.

1/spl times/2 and 1/spl times/4 electrooptic switches

We describe the design, fabrication, and testing of two packaged electrooptic switches built from poled LiTaO/sub 3/ crystals. The 1/spl times/2 switch requires a driving voltage of 1200 V and exhibits insertion loss of 2.4 dB and crosstalk of -39.2 dB; the 1/spl times/4 switch exhibits insertion loss and crosstalk of 2.8 dB and -40.6 dB, respectively, and operates using a 1100-V voltage source. The maximum deflection time between the channels is 86 ns.

Design of a fully integrated array of high-voltage digital-to-analog converters

The first fully integrated array of high voltage (HV) digital-to-analog converters (DACs) was designed in DALSA Semiconductors 0.8 /spl mu/m CMOS/DMOS HV process technology. The 6-bit 300 V DACs are based on a current-steering, thermometer coded architecture and show a DNL (differential nonlinearity) of 0.16 LSB and an INL (integral nonlinearity) of 0.18 LSB. The current-to-high-voltage conversion is done using a high-compliance current mirror adapted to the HV technology, as traditional output resistor or op-amp solutions are not optimum for the HV process. The design is suited for applications requiring a set of digitally-controlled high-voltage signals.

Test setup for optical burst-mode receivers

This paper proposes a test setup that can accurately measure the lock acquisition time of conventional and burst mode receivers subjected to phase, frequency, or amplitude steps. This work will be useful to network architects and circuit designers who wish to know with precision how many bits a receiver needs to acquire lock. The technique for measuring lock acquisition time, or preamble length, is based on an acceptable BER for the payload. Measurement results for the lock acquisition time of two commercially available OC-48 receiver chips will be presented.

Reprogrammable optical phase array

A novel reprogrammable optical phase array (ROPA) device is presented as a reconfigurable electro-optic element. One specific application of the ROPA, a 1 x 6 electro-optic space switch, is fully described. Switching angles are within 2 degrees , and switching is achieved through a complementary metal-oxide semiconductor (CMOS) controlled, diffraction based, optical phase array in a bulk BaTiO3 crystal. The crystal is flip-chipped to the CMOS chip, creating a compact fully integrated device. The design, optical simulation, and fabrication of the device are described, and preliminary experimental results are presented.

1-Gb/s 9 X 1 optical receiver array for an adaptive redundant interconnect system using NT25 technology

This paper presents the design of a receiver used in a self- aligning optical interconnect. We have made use of spatial redundancy to increase the misalignment tolerance of a system of four 1 Gb/s free-space optical links. The receiver for this system is a rapidly re-configurable array that accepts nine low-amplitude, high-speed photocurrents, selects one of them, and then outputs that signal as a digital differential positive emitter coupled logic signal. The selection of which channel to amplify is based on received power, and is performed off-chip. Preliminary results indicate that the receiver performs with a low bit error rate up to 750 Mb/s.

1.25-Gb/s transmitter for an adaptive redundant free-space optical interconnect

In order to provide a reliable optical link, the emitters and detectors within a free-space optical interconnect need to be aligned to each other within tight tolerances. Typical methods to achieve this alignment involve the use of precision optomechanics or active steering elements. An alternative approach to the alignment problem is to use spatial redundancy. One way to accomplish this is by increasing the number of possible optical links and using only a subset of those links to provide reliable high-speed channels. This paper presents the design and testing of a high speed transmitter chip developed for an adaptive redundant optical interconnect system. Optoelectronic design and device packaging will also be described.

Reprogrammable optical phase array (ROPA) for use in an agile all-photonic network

The design and simulation of a 1×N optical switch is presented. Sub-¿s switching is achieved through a voltage-controlled optical phase array. Electrode voltages are provided by a high-voltage CMOS chip. Switching angles are within 2°.

5-Gb/s 2-channel bidirectional adaptive redundant FSOI demonstrator system

A novel board-to-board free space optical interconnect which operates on the principle of redundancy is described. Tolerance to misalignment is achieved through the use of 2D arrays of lasers and detectors together with an adaptive alignment algorithm based on redundant transceivers and a defocused optical interconnect. In this system, four 1.25 Gb/s data channels are supported by transmitter modules and receiver modules (2 per board) which contain 3 X 3 VCSEL and 3 X 3 photodiode arrays, respectively. The system was designed to have lateral misalignment tolerance of +/- 1 mm and angular tolerance of +/- 1 degree(s).