M. Morel

Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond

The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 μm×425 μm pixel cells in the 256×32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32×32 array of 400 μm×425 μm cells. Radiation tolerance was enhanced through special circuit layout. Sensitivity to coupling of digital signals into the analog front end was minimized. System issues such as testability and uniformity further constrained the design. The circuit is currently being manufactured in a commercial 0.25 μm CMOS technology.

The ALICE on-Detector pixel PILOT system-OPS

The on-detector electronics of the ALICE silicon pixel detector (nearly 10 million pixels) consists of 1,200 readout chips, bump-bonded to silicon sensors and mounted on the front-end bus, and of 120 control (PILOT) chips, mounted on a multi chip module (MCM) together with opto-electronic transceivers. The environment of the pixel detector is such that radiation tolerant components are required. The front-end chips are all ASICs designed in a commercial 0.25-micron CMOS technology using radiation hardening layout techniques. An 800 Mbit/s Glink-compatible serializer and laser diode driver, also designed in the same 0.25 micron process, is used to transmit data over an optical fibre to the control room where the actual data processing and event building are performed. We describe the system and report on the status of the PILOT system.

The ALICE Silicon Pixel Detector: readiness for the first proton beam

The Silicon Pixel Detector (SPD) is the innermost element of the ALICE Inner Tracking System (ITS). The SPD consists of two barrel layers of hybrid silicon pixels surrounding the beam pipe with a total of ≈ 107 pixel cells. The SPD features a very low material budget, a 99.9% efficient bidimensional digital response, a 12 μm spatial precision in the bending plane (r) and a prompt signal as input to the L0 trigger. The SPD commissioning in the ALICE experimental area is well advanced and it includes calibration runs with internal pulse and cosmic ray runs. In this contribution the commissioning of the SPD is reviewed and the first results from runs with cosmic rays and circulating proton beams are presented.

Irradiation and SPS Beam Tests of the Alice1LHCb Pixel Chip

The Alice1LHCb front-end chip [1,2] has been designed for the ALICE pixel and the LHCb RICH detectors. It is fabricated in a commercial 0.25 μm CMOS technology, with special design techniques to obtain radiation tolerance. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets (SEU), and with X-rays to evaluate the sensitivity to total ionising dose. We report the results of those measurements. We also report preliminary results of measurements done with 150 GeV pions at the CERN SPS.

The ALICE Pixel Detector Readout Chip Test System

The ALICE experiment will require some 1200 Readout Chips for the construction of the Silicon Pixel Detector [1] and it has been estimated that approximately 3000 units will require testing. This paper describes the system that was developed for this task.

A pixel readout chip for 10-30 Mrad in standard 0.25 /spl mu/m CMOS

A radiation tolerant pixel detector readout chip has been developed in a commercial 0.25 /spl mu/m CMOS process. The chip is a matrix of two columns of 65 identical cells. Each readout cell comprises a preamplifier, a shaper filter, a discriminator, a delay line and readout logic. The chip occupies 10 mm/sup 2/, and contains about 50000 transistors. Electronic noise (/spl sim/220 e rms) and threshold dispersion (/spl sim/160 e rms) allow operation at 1500 e average threshold. The radiation tolerance of this mixed mode analog-digital circuit has been enhanced by designing NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The chip, which was developed at CERN for the ALICE and LHCb experiments, was still operational after receiving 3.6/spl times/10/sup 13/ protons over an area of 2/spl times/2 mm. Other chips were irradiated with X-rays and remained fully functional up to 30 Mrad (SiO/sub 2/) with only minor changes in analog parameters. These results indicate that careful use of deep submicron CMOS technologies can lead to circuits with high radiation tolerance.

The electro-mechanical integration of the NA62 GigaTracker time tagging pixel detector

The NA62 GigaTracker is a low mass time tagging hybrid pixel detector operating in a beam with a particle rate of 750 MHz. It consists of three stations with a sensor size of 60 x 27mm(2) containing 18000 pixels, each 300 x 300 mu m(2). The active area is connected to a matrix of 2 x 5 pixel ASICs, which time tag the arrival of the particles with a binning of 100 ps. The detector operates in vacuum at -20 to 0 degrees C and the material budget per station must be below 0.5% X-0. Due to the high radiation environment of 2 x 10(14) 1 MeV neutron equivalent cm(-2)/yr(-1) it is planned to exchange the detector modules regularly. The low material budget, cooling requirements and the request for easy module access has driven the electro-mechanical integration of the GigaTracker, which is presented in this paper.

Test-beam results of a silicon pixel detector with Time-over-Threshold read-out having ultra-precise time resolution

A time-tagging hybrid silicon pixel detector developed for beam tracking in the NA62 experiment has been tested in a dedicated test-beam at CERN with 10 GeV/c hadrons. Measurements include time resolution, detection efficiency and charge sharing between pixels, as well as effects due to bias voltage variations. A time resolution of less than 150 ps has been measured with a 200 μm thick silicon sensor, using an on-pixel amplifier-discriminator and an end-of-column DLL-based time-to-digital converter.

A 9-Channel, 100 ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix)

The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station of the Gigatracker needs to provide time stamping of individual particles to 200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x 40 pixels. The high precision time measurement of the discriminated hit signals is accomplished with a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9 channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approach is employed to achieve a constant time binning of 100ps. Simulation results show that an average rms time resolution of 33ps with a power consumption of the TDC better than 33 mW per column is achieved. This contribution will present the design, simulation results and implementation challenges of the TDC.

A pixel readout chip for 10-30 Mrad in standard 0.25 μm CMOS

A radiation tolerant pixel detector readout chip has been developed in a commercial 0.25 /spl mu/m CMOS process. The chip is a matrix of two columns of 65 identical cells. Each readout cell comprises a preamplifier, a shaper filter, a discriminator, a delay line and readout logic. The chip occupies 10 mm/sup 2/, and contains about 50000 transistors. Electronic noise (/spl sim/220 e rms) and threshold dispersion (/spl sim/160 e rms) allow operation at 1500 e average threshold. The radiation tolerance of this mixed mode analog-digital circuit has been enhanced by designing NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The chip, which was developed at CERN for the ALICE and LHCb experiments, was still operational after receiving 3.6/spl times/10/sup 13/ protons over an area of 2/spl times/2 mm. Other chips were irradiated with X-rays and remained fully functional up to 30 Mrad (SiO/sub 2/) with only minor changes in analog parameters. These results indicate that careful use of deep submicron CMOS technologies can lead to circuits with high radiation tolerance.