M. Narihiro

Kishou Kaneko; H. Sunamura; M. Narihiro; S. Saito; N. Furutake; Masami Hane; Y. Hayashi

Functional circuit elements based on novel BEOL-transistors with a wide-band-gap oxide semiconductor InGaZnO (IGZO) film are integrated onto LSI Cu-interconnects, and their operations are demonstrated. High-current comb-type transistors show excellent Ion/Ioff ratio (>;108) and high-Vd operation with linear area dependence, realizing area-saving compact high-current BEOL switches. Successful operation of voltage-controlled inverter switches with high-Vd enables on-chip bridging I/Os between high/low voltage on conventional Si system LSIs. Setting the gate-to-drain offset design to just 0.1μm realizes +20V enhancement of the breakdown voltage to ~60V with excellent safety operation at around Vd=50V due to the wide-band-gap characteristics.

Munehiro Tada; Y. Harada; T. Tamura; Naoya Inoue; Fuminori Ito; M. Yoshiki; H. Ohtake; M. Narihiro; M. Tagami; Makoto Ueki; K. Hijioka; M. Abe; Tsuneo Takeuchi; S. Saito; T. Onodera; N. Furutake; K. Arai; K. Fujii; Y. Hayashi

A highly reliable, 65 nm-node Cu interconnect technology has been developed with 180 nm/200 nm-pitched lines connected through /spl phi/100 nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-infra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB (time dependent dielectric breakdown) reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65 nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.

H. Sunamura; Kishou Kaneko; N. Furutake; S. Saito; M. Narihiro; Nobuyuki Ikarashi; Masami Hane; Y. Hayashi

A new P-type amorphous SnO thin-film transistor with high I_on/I_off ratio of >10⁴ is developed, for the first time, as a component to complement N-type IGZO transistors for on-chip voltage-bridging BEOL-CMOS I/Os on conventional Si-LSI Cu-interconnects (Fig. 1). Dedicated low-temperature (<;400°C) oxide-semiconductor processes are implemented to overcome several integration challenges (Fig. 2) with only one-mask addition using standard BEOL process tools (Fig. 3). We demonstrate high I_on/I_off ratio of >10⁴ and high-V_d capability (|V_bd|>40V) with gate-to-drain offset structure, showing superior properties over the previously reported values (Table 1). The SnO transistor is suited for the BEOL-CMOS I/O, which gives standard LSIs a special add-on function to control high voltage signals directly in smart society applications.

K. Hijioka; J. Kawahara; M. Narihiro; I. Kume; A. Tanabe; H. Nagase; H. Yamamoto; Naoya Inoue; Tsuneo Takeuchi; T. Onodera; S. Saito; N. Furutake; Y. Hayashi

A new partially-thickened local (PTL)-interconnect structure with an extremely low resistance is developed for the 40 nm-node low-power CMOS device to boost the RF performance. The PTL-interconnect is featured by the Cu dual-damascene (DD) interconnect combined with the slit-contact (SLICT) in the low-k pre-metal-dielectrics (PMD, k=3.1), accomplishing 50% reduction in the resistance of metal-1 (M1), and the contact resistance between M1 and the gate silicide-interconnect also decreased remarkably. The maximum oscillation frequency (fmax), which is influenced strongly by the effective gate resistance as an input signal port, increased 30% referred to that with conventional W-pillar contacts in the SiO2-PMD. The low-resistance PTL-interconnect backed with the Cu-DD SLICT in the low-k PMD is essential for low-power RF/mixed-signal SoCs.

H. Sunamura; Naoya Inoue; N. Furutake; S. Saito; M. Narihiro; Masami Hane; Y. Hayashi

Enhanced current drivability of BEOL-process-compatible dual-oxide complementary BEOL-FETs on LSI-interconnects (Fig. 1) with just two additional masks to the state-of-the-art BEOL process is demonstrated, aiming at high-Vbd pre-driver operation. We have developed processes so that IGZO-based NFETs have lower ARon as compared to currently available Si power devices (Fig. 6). We also developed new SnO processes, realizing a 30× Ion boost for PFETs. Dual oxide semiconductor channels are integrated to form BEOL-CMOS inverters with stable and sharp cut-off characteristics (Figs. 8 and 9) for lower power operation, leading to a successful operation of an integrated 6T-SRAM cell (Fig. 11). Pre-driver capability of NFET inverters is demonstrated with MCU-controlled operation of brushless DC (BLDC) motors (Fig. 12). This technology is a strong candidate to realize high-Vbd pre-drivers and low-power logic on BEOL, which gives standard LSIs a special add-on function for smart society applications.

Nobuyuki Ikarashi; M. Narihiro; T. Hase

LSI Research Laboratory, Renesas Electronics Corporation 1120 Shimokuzawa, Chuou-ku, Sagamihara, 252-5298, Japan E-mail: nobuyuki.ikarashi.xz@renesas.com

M. Tagami; H. Ohtake; Munehiro Tada; Makoto Ueki; Fuminori Ito; T. Taiji; Y. Kasama; T. Iwamoto; H. Wakabayashi; T. Fukai; K. Arai; Shinsaku Saito; H. Yamamoto; M. Abe; M. Narihiro; N. Furutake; T. Onodera; Tsuneo Takeuchi; Y. Tsuchiya; Noriaki Oda; M. Sekine; M. Hane; Y. Hayashi

H. Sunamura; Kishou Kaneko; N. Furutake; Shinsaku Saito; M. Narihiro; Masami Hane; Y. Hayashi

Nobuyuki Ikarashi; M. Narihiro

M. Ueki; Y. Hayashi; N. Furutake; Koji Masuzaki; Akira Tanabe; M. Narihiro; H. Sunamura; Kazuya Uejima; Akira Mitsuiki; Koichi Takeda; Takashi Hase