M. Nirmala Devi

A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis

Hardware Trojan Horses have emerged as great threats to modern electronic design and manufacturing practices. Because of their inherent surreptitious nature, test vector generation to detect hardware Trojan horses is a difficult problem. Efficient online detection techniques can be more effective in detection of hardware Trojan horses. In this paper, we propose a low-overhead detection technique which inserts malicious logic detection circuitry at netlist sites chosen by an algorithm that employs an intelligent and accurate analysis of fault propagation through logic gates. Proactive system-level countermeasures can be activated on detection of malicious logic, thereby avoiding disastrous system failure. Experimental results on benchmark circuits show close to 100 percent HTH detection coverage when our proposed technique is employed, as well as acceptable overheads.

VLSI Architecture for Compressed Domain Video Watermarking

Digital watermarking has become very important for protecting the authenticity of multimedia objects as they become easier to copy, exchange, and modify due to the large diffusion of powerful personal computers. The video has been utilized in a variety of applications such as video editing, Internet video distribution, wireless video communications etc. Some of these applications are likely to get great benefit from video watermarking technology. Main objective of this research is to design robust perceptual video watermarking targeted at achieving better performance and reliability. Due to its robust nature, Discrete Cosine Transform (DCT) watermarking was chosen in this work to accomplish video copyright protection. The watermark is inserted in the video stream during compression, resulting in an optimized compression/watermarking algorithm and system.

Malicious Circuit Detection for Improved Hardware Security

Hardware Trojans have become a major threat faced by most of the VLSI fabrication houses. This paper proposes a non-destructive method for Hardware Trojan detection. Since in many cases the golden chip is unavailable and hence voting technique is adopted.This paper is an extension of the weighed voting. A microcontroller based portable standalone system that will identify any malicious activity in a circuit was designed and implemented. This standalone system performs the weighed voting to detect any malicious activity of the Circuit under Test implemented in FPGA. The working of this standalone system was tested and validated by using ISCAS ‘85 Benchmark circuits implemented in Spartan 6 XC6SLX16 FPGA. The accuracy was around 93.93 % while testing the system. A novel hardware based solution for hardware Trojan detection is attempted in this work.

Computer-aided Diagnosis of Breast Cancer by Hybrid Fusion of Ultrasound and Mammogram Features

Ultrasound images are increasingly being used as an important adjunct to X-ray mammograms for diagnosis of breast cancer. In this paper, a computer-aided diagnosis system that utilizes a hybrid fusion strategy based on canonical correlation analysis (CCA) is proposed for discriminating benign and malignant masses. The system combines information from three different sources, i.e., ultrasound and two views of mammogram, namely, mediolateral oblique (MLO) and craniocaudal (CC) views. CCA is employed on ultrasound-MLO and ultrasound-CC feature pairs to explore the hidden correlations between ultrasound and mammographic view. The two pairs of canonical variates are fused at the feature level and given as input to support vector machine (SVM) classifiers. Finally, decisions of the two classifiers are fused. Results show that the proposed system outperforms unimodal systems and state-of-the-art fusion strategies.

Improvisation of particle swarm optimization algorithm

The improvised Particle Swarm Optimization (PSO) Algorithm offers better search efficiency than conventional PSO algorithm. It provides an efficient technique to obtain the best optimized result in the search space. This algorithm ensures a faster rate of convergence to the desired solution whose precision can be preset by the user. The inertia parameter is varied linearly with iteration number, which results in more accurate solution for unimodal functions. The control over the precision value acts as a trade-off between the convergence time and precision of the desired solution, and it can be viewed as a performance parameter. Swarm convergence is followed by a mutation process, which further improves the obtained result by enhancing the local search ability of some particles. The results show that the solution with predefined precision level can be obtained with the minimum number of iterations.

Hardware Implementation of SVD Based Colour Image Watermarking in Wavelet Domain

While it has become very easy to process and store digital images effectively, it has also paved way for ease in illegal production and redistribution. Watermarking is the best way to protect digital image against illegal recording and distribution. From the literature survey, it has been affirmed that the frequency domain techniques are more robust than spatial domain techniques. In this paper a singular value decomposition (SVD) based watermarking is executed in wavelet domain. This paper proposes the design and hardware implementation of a fast RGB to YUV converter by standard NTSC conversion and reconstruction formulae using optimal 2-D systolic arrays for matrix multiplication.The scheme have been implemented in Altera Cyclone II FPGA. The hardware implementation of 2D DWT decomposition and IDWT reconstruction were implemented in Xilinx xc3s1000-4fg320. Watermarks inserted in the lowest frequencies (LL subband) are resistant to certain group of attacks, and watermarks embedded in highest frequencies (HH subband) are resistant to another group of attacks. Embedding the same watermark in all 4 blocks, will make it extremely difficult to remove or destroy the watermark from all frequency subbands. The proposed algorithm is less resilient to geometric distortion including rotation, scaling and translation. The hardware implementation watermarking schemes has advantages over the software implementation in terms of high performance, and reliability. A hybrid SVD image watermarking in wavelet domain, will have more robustness.

Design and analysis of GaN HEMT based LNA with CPW matching

GaN based devices are in great demand due to its rugged characteristics at extreme conditions. In this paper, design of GaN monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) with coplanar waveguide matching is presented to understand the key aspects of high gain, low noise figure and high linearity. The LNA can be used in base station technologies as frequency of interest is from 0.6-3 GHz. It delivers gain of 23 dB and noise figure 0.3 dB and OIP3 upto 51 dBm. The linear performance presented here enables reconfigurable designs of LNA over multiple octaves of bandwidth.

Small signal modelling of GaN HEMT at 70GHz

A new 18-element small-signal model for GaN high electron mobility transistor is presented to operate at very high frequencies around 70 GHz. This model accounts for the need of a capacitor to represent the capacitive effect between the end of the drain electrode and contacting pad of the gate electrode. An extrinsic parasitic gate-drain capacitance as for higher frequencies this parameter becomes significant even under cold-FET conditions. This novel approach compensates for the high linear dependency of inductance at such high frequencies and the improved performance is evident in the S-parameter modelled. The validity of the proposed model has been well-illustrated up to 100 GHz frequency by the modelled S-parameters.

Efficient linear feedback shift register design for pseudo exhaustive test generation in BIST

Pattern generation is the most important module in a BIST. Out of many test pattern generators (TPG) explored for BIST, linear feedback shift registers (LFSR) are widely used due to their ability to produce highly random patterns. Various improvements over the basic forms of LFSR are available. In the current study, the selection of an appropriate LFSR for a given benchmark circuit is analyzed. It is done by considering various factors such as selection of characteristic polynomial and seed to obtain high fault coverage, minimize invalid patterns, area overhead and time taken to generate the patterns.

Velocity Restriction-Based Improvised Particle Swarm Optimization Algorithm

The Particle Swarm Optimization (PSO) Algorithm attempts on the use of an improved range for inertia weight, social, and cognitive factors utilizing the Pareto principle. The function exhibits better convergence and search efficiency than PSO algorithms that use conventional linearly varying or exponentially varying inertia weights. It also presents a technique to intelligently navigate the search space around the obtained optima and looks for better optima if available and continue converging with the new values using a velocity restriction factor based on the Pareto principle. The improvised algorithm searches the neighborhood of the global optima while maintaining frequent resets in the position of some particles in the form of a mutation based on its escape probability. The results have been compared and tabulated against popular PSO with conventional weights and it has been shown that the introduced PSO performs much better on various benchmark functions.